전자부품 데이터시트 검색엔진 |
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AD7864 데이터시트(PDF) 4 Page - Analog Devices |
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AD7864 데이터시트(HTML) 4 Page - Analog Devices |
4 / 19 page AD7864 –4– REV. A TIMING CHARACTERISTICS1, 2 Parameter A, B Versions Units Test Conditions/Comments tCONV 1.65 µs max Conversion Time, Internal Clock 13 Clock Cycles Conversion Time, External Clock 2.6 µs max CLKIN = 5 MHz tACQ 0.34 µs max Acquisition Time tBUSY No. of Channels Selected Number of Channels Multiplied by x (tCONV + t9) – t9 µs max (tCONV + EOC Pulsewidth)—EOC Pulsewidth tWAKE-UP—External VREF 2 µs max STBY Rising Edge to CONVST Rising Edge tWAKE-UP—Internal VREF 3 6ms max STBY Rising Edge to CONVST Rising Edge t1 35 ns min CONVST Pulsewidth t2 70 ns min CONVST Rising Edge to BUSY Rising Edge Read Operation t3 0 ns min CS to RD Setup Time t4 0 ns min CS to RD Hold Time t5 35 ns min Read Pulsewidth t6 4 35 ns max Data Access Time After Falling Edge of RD, V DRIVE = 5 V 40 ns max Data Access Time After Falling Edge of RD, V DRIVE = 3 V t7 5 5 ns min Bus Relinquish Time After Rising Edge of RD 30 ns max t8 10 ns min Time Between Consecutive Reads t9 75 ns min EOC Pulsewidth 180 ns max t10 70 ns max RD Rising Edge to FRSTDATA Edge (Rising or Falling) t11 15 ns max EOC Falling Edge to FRSTDATA Falling Delay t12 0 ns min EOC to RD Delay Write Operation t13 20 ns min WR Pulsewidth t14 0 ns min CS to WR Setup Time t15 0 ns min WR to CS Hold Time t16 5 ns min Input Data Setup Time of Rising Edge of WR t17 5 ns min Input Data Hold Time NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2See Figures 7, 8 and 9. 3Refer to the Standby Mode Operation section. The MAX specification of 6 ms is valid when using a 0.1 µF decoupling capacitor on the V REF pin. 4Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice. (VD = +5 V 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications TMIN to TMAX unless otherwise noted.) TO OUTPUT 50pF 1.6V 400 A 1.6mA Figure 1. Load Circuit for Access Time and Bus Relinquish Time |
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