ADV476

REV. B

–3–

Parameter

66 MHz Version

50 MHz Version

35 MHz Version

Units

Conditions/Comments

66

50

35

MHz

Clock Rate

10

10

15

ns min

RS0, RS1 Setup Time

10

10

15

ns min

RS0, RS1 Hold Time

5

5

5

ns min

RD

Asserted to Data Bus Driven

40

40

40

ns max

RD

Asserted to Data Valid

20

20

20

ns max

RD

Negated to Data Bus 3-Stated

10

10

15

ns min

Write Data Setup Time

10

10

15

ns min

Write Data Hold Time

50

50

50

ns min

RD

, WR Pulse Width Low

ns min

RD

, WR Pulse Width High

3

3

4

ns min

Pixel & Control Setup Time

3

3

4

ns min

Pixel & Control Hold Time

15.3

20

28

ns min

Clock Cycle Time

5

6

7

ns min

Clock Pulse Width High Time

5

6

9

ns min

Clock Pulse Width Low Time

30

30

30

ns max

Analog Output Delay

5

5

5

ns min

6

8

8

ns max

Analog Output Rise/Fall Time

3

15.3

20

25

ns typ

Analog Output Settling Time

2

2

2

ns min

Analog Output Skew

4

4

4

clocks

Pipeline Delay

NOTES

≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load

≤10 pF, 37.5 Ω. D0–D7 output load ≤50 pF. See timing notes in Figure 2.

Ω resistor to ground and are driven by 74HC logic.

Specifications subject to change without notice.

Figure 1. MPU Read/Write Timing

Figure 2. Video Input/Output Timing