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ADV7123JST330 데이터시트(PDF) 7 Page - Analog Devices |
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ADV7123JST330 데이터시트(HTML) 7 Page - Analog Devices |
7 / 20 page –7– REV. B ADV7123 3.3 V TIMING SPECIFICATIONS 1 Parameter Min Typ Max Unit Condition ANALOG OUTPUTS Analog Output Delay, t6 7.5 ns Analog Output Rise/Fall Time, t7 4 1.0 ns Analog Output Transition Time, t8 5 15 ns Analog Output Skew, t9 6 12 ns CLOCK CONTROL fCLK 7 50 MHz 50 MHz Grade fCLK 7 140 MHz 140 MHz Grade fCLK 7 240 MHz 240 MHz Grade fCLK 7 330 MHz 330 MHz Grade Data and Control Setup, t1 0.2 ns Data and Control Hold, t2 1.5 ns Clock Pulsewidth High, t4 6 1.4 ns fCLK_MAX = 330 MHz Clock Pulsewidth Low, t5 6 1.4 ns fCLK_MAX = 330 MHz Clock Pulsewidth High, t4 1.875 ns fCLK_MAX = 240 MHz Clock Pulsewidth Low t5 1.875 ns fCLK_MAX = 240 MHz Clock Pulsewidth High t4 2.85 ns fCLK_MAX = 140 MHz Clock Pulsewidth Low t5 2.85 ns fCLK_MAX = 140 MHz Clock Pulsewidth High t4 8.0 ns fCLK_MAX = 50 MHz Clock Pulsewidth Low t5 8.0 ns fCLK_MAX = 50 MHz Pipeline Delay, tPD 6 1.0 1.0 1.0 Clock Cycles PSAVE Up Time, t 10 6 410 ns NOTES 1Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies. 2These maximum and minimum specifications are guaranteed over this range. 3Temperature range: T MIN to TMAX: –40 °C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz. 4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5Measured from 50% point of full-scale transition to 2% of final value. 6Guaranteed by characterization. 7f CLK max specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization. Specifications subject to change without notice. t2 CLOCK DATA NOTES 1. OUTPUT DELAY ( t 6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME ( t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. 3. TRANSITION TIME ( t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. ANALOG OUTPUTS (IOR, IOR, IOG, IOG, IOB, IOB) DIGITAL INPUTS (R9–R0, G9–G0, B9–B0, SYNC, BLANK) t3 t4 t5 t1 t8 t6 t7 Figure 1. Timing Diagram (VAA = 3.0 V–3.6 V 2, V REF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications TMIN to TMAX 3, unless otherwise noted, T J MAX = 110 C.) |
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