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ADV7196AKS 데이터시트(PDF) 11 Page - Analog Devices |
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ADV7196AKS 데이터시트(HTML) 11 Page - Analog Devices |
11 / 36 page REV. 0 ADV7196A –11– Input/Output Configuration Table I shows possible input/output configurations when using the ADV7196A. Table I. Input Format Output YCrCb Progressive Scan 4:2:2 2 × 4:4:4 1 × or 2× YCrCb HDTV 4:2:2 1 × 4:4:4 1 × RGB Progressive Scan 4:4:4 2 × RGB HDTV 4:4:4 1 × Async Timing Mode All Inputs 1 × 10 0 –80 –40 –50 –60 –70 –20 –30 –10 5 10152025 0 30 Figure 8. 2 × Interpolation Filter – Y-Channel 10 0 –80 –40 –50 –60 –70 –20 –30 –10 5 10152025 0 30 Figure 9. Interpolation Filter – CrCb Channels for 4:2:2 Input Data 10 0 –80 –40 –50 –60 –70 –20 –30 –10 5 10152025 0 30 Figure 10. Interpolation Filter – CrCb Channels for 4:4:4 Input Data MPU PORT DESCRIPTION The ADV7196A support a 2-wire serial (I 2C-compatible) micro- processor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7196A has four possible slave addresses for both read and write operations. These are unique addresses for each device and illustrated in Figure 11. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write opera- tion. A1 is set by setting the ALSB pin of the ADV7196A to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater input bandwidth on the I 2C lines, which allows high- speed data transfers on this bus. When ALSB is set to “1,” there is reduced input bandwidth on the I 2C lines, which means that pulses of less than 50 ns will not pass into the I 2C internal control- ler. This mode is recommended for noisy systems. 1 X 1 0 1 01 A1 ADDRESS CONTROL SET UP BY ALSB READ/ WRITE CONTROL 0 WRITE 1READ Figure 11. Slave Address To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a Start condition, defined by a high-to-low transi- tion on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-bit address + R/ W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the Start condition and the correct transmitted address. The R/ W bit determines the direction of the data. |
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