OP183 datasheet(3/12 Pages) AD

부품명	OP183

상세설명	5 MHz Single-Supply Operational Amplifiers

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REV.B

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

V

OS

0.01

1.0

mV

–40

°C ≤ T

A ≤ +85°C

1.25

mV

Input Bias Current

I

B

300

600

nA

–40

°C ≤ T

A ≤ +85°C

400

750

nA

Input Offset Current

I

OS

–40

≤ T

A ≤ +85°C11

±50

nA

Input Voltage Range

–15

+13.5

V

Common-Mode Rejection Ratio

CMRR

V

CM = –15 V to +13.5 V,

–40

°C ≤ T

A ≤ +85°C70

86

dB

Large Signal Voltage Gain

A

VO

R

L = 2 kΩ

100

1000

V/mV

Offset Voltage Drift

∆V

OS/∆T3

µV/°C

Bias Current Drift

∆I

B/∆T

–1.6

nA/

°C

Long Term Offset Voltage

V

OS

Note 1

1.5

mV

OUTPUT CHARACTERISTICS

Output Voltage High

V

OH

R

L = 2 kΩ to GND, –40°C ≤ TA ≤ +85°C

+13.9 14.1

V

Output Voltage Low

V

OL

R

L = 2 kΩ to GND, –40°C ≤ TA ≤ +85°C

–14.05

–13.9

V

Short-Circuit Limit

I

SC

Source

30

mA

Sink

50

mA

Open -Loop Output Impedance

Z

OUT

f = 1 MHz, A

V = +1

15

Ω

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

V

S = ± 2.5 V to ± 18 V,

–40

°C ≤ T

A ≤ +85°C

70

112

dB

Supply Current/Amplifier

I

SY

V

S = ± 18 V, VO = 0 V,

–40

°C ≤ T

A ≤ +85°C

1.2

1.75

mA

Supply Voltage Range

V

S

+3

±18

V

DYNAMIC PERFORMANCE

Slew Rate

SR

R

L = 2 kΩ

10

15

V/

µs

Full-Power Bandwidth

BW

p

1% Distortion

50

kHz

Settling Time

t

S

To 0.01%

1.5

µs

Gain Bandwidth Product

GBP

5

MHz

Phase Margin

φm

56

degrees

NOISE PERFORMANCE

Voltage Noise

e

n p-p

0.1 Hz to 10 Hz

2

µV p-p

Voltage Noise Density

e

n

f = 1 kHz

10

nV/

√Hz

Current Noise Density

i

n

0.4

pA/

√Hz

NOTES

1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125

°C, with an LTPD of 1.3.

Specifications subject to change without notice.

(@ V

S =

15.0 V, T

A = +25 C unless otherwise noted)

WAFER TEST LIMITS

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

V

OS

V

S = ± 15 V, VO = 0 V

1.0

mV max

Input Bias Current

I

B

V

CM = 2.5 V

±600

nA max

Input Offset Current

I

OS

V

CM = 2.5 V

±50

nA max

Common-Mode Rejection

CMRR

V

CM = 0 V to 3.5 V

70

dB min

Power Supply Rejection Ratio

PSRR

V =

±2.5 V to ±18 V

70

dB min

Large Signal Voltage Gain

A

VO

R

L = 2 kΩ, 0.2 ≤ VO

≤ 3.8 V

100

V/mV min

Output Voltage High

V

OH

R

L = 2 kΩ

4.0

V min

Output Voltage Low

V

OL

R

L = 2 kΩ

75

mV max

Supply Current/Amplifier

I

SY

V

S = ± 15 V, VO = 0 V, RL =

∞

1.5

mA max

NOTE

Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard

product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

(@ V

S = +5.0 V, TA = +25 C unless otherwise noted)

OP183/OP283

–3–

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