전자부품 데이터시트 검색엔진 |
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SSM-2005 데이터시트(PDF) 10 Page - Analog Devices |
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SSM-2005 데이터시트(HTML) 10 Page - Analog Devices |
10 / 15 page SSM2005 –10– REV. 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 DATA 0 1 0 1 0 CLK DATA tCL CLK 1 tCH tDS tDH tWC tCW tW3 WRITE & LOAD WRITE & LOAD 1 0 Figure 7. Logic Timing Diagram Table IV. Timing Description Timing Symbol Description Min Typ Max Units tCL Input Clock Pulsewidth 50 ns tCH Input Clock Pulsewidth 50 ns tDS Data Setup Time 25 ns tDH Data Hold Time 35 ns tCW Positive CLK Edge to End of Write 25 ns tWC Write to Clock Setup Time 35 ns tLW End of Load Pulse to Next Write (4-Wire Mode) 20 ns tWL End of Write to Start of Load (4-Wire Mode) 20 ns tL Load Pulsewidth (4-Wire Mode) 250 ns tW3 Load Pulsewidth (3-Wire Mode) 250 ns NOTES: 1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the positive edge. 2. For SPI TM or MICROWIRETM 3-wire bus operation, tie LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal LD signal.) 3. If an idle HI clock is used, tCW and tWL are measured from the final negative transition to the idle state. 4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain levels. Refer to the Address/Data Decoding Truth Table. 5. Data must be sent MSB first. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. |
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