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74ABT126 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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74ABT126 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2005 Fairchild Semiconductor Corporation DS011692 www.fairchildsemi.com January 1995 Revised February 2005 74ABT126 Quad Buffer with 3-STATE Outputs General Description The ABT126 contains four independent non-inverting buff- ers with 3-STATE outputs. Features s Non-inverting buffers s Output sink capability of 64 mA, source capability of 32 m s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Pin Descriptions Function Table H HIGH Voltage Level L LOW Voltage Level Z HIGH Impedance X Immaterial Order Number Package Package Description Number 74ABT126CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ABT126CSJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT126CMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT126CMTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Descriptions An, Bn Inputs On Outputs Inputs Output An Bn On HL L HH H LX Z |
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