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2

Functional Description

The ACT825 consists of eight D-type edge-triggered flip-

flops. These devices have 3-STATE outputs for bus sys-

tems, organized in a broadside pinning. In addition to the

clock and output enable pins, the buffered clock (CP) and

buffered Output Enable (OE) are common to all flip-flops.

The flip-flops will store the state of their individual D inputs

that meet the setup and hold time requirements on the

LOW, the contents of the flip-flops are available at the out-

go to the high impedance state.

Operation of the OE input does not affect the state of the

flip-flops. The ACT825 has Clear (CLR) and Clock Enable

(EN) pins. These pins are ideal for parity bus interfacing in

high performance systems.

When CLR is LOW and OE is LOW, the outputs are LOW.

When CLR is HIGH, data can be entered into the flip-flops.

When EN is LOW, data on the inputs is transferred to the

outputs on the LOW-to-HIGH clock transition. When EN is

HIGH, the outputs do not change state, regardless of the

data or clock input transitions.

Function Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance

 = LOW-to-HIGH Transition

NC

= No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs

Internal

Output

Function

OE

CLR

EN

CP

QO

HX

L



L

L

Z

High-Z

HX

L



H

H

Z

High-Z

H

L

XXX

L

Z

Clear

L

L

XXX

L

L

Clear

H

H

H

X

X

NC

Z

Hold

LH

H

X

X

NC

NC

Hold

HH

L



L

L

Z

Load

HH

L



H

H

Z

Load

LH

L



L

L

L

Load

LH

L



H

H

H

Load