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74F258ASC 데이터시트(PDF) 2 Page - Fairchild Semiconductor

부품명 74F258ASC
상세설명  Quad 2-Input Multiplexer with 3-STATE Outputs
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
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Unit Loading/Fan Out
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
Functional Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I0x inputs are selected and when Select
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in inverted form.
The 74F258A is the logic implementation of a 4-pole, 2-
position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equation for the outputs is shown below:
Z n = OE • (I1n • S + I0n • S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs of
the 3-STATE devices are tied together, all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
S
Common Data Select Input
1.0/1.0
20
µA/−0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
I0a–I0d
Data Inputs from Source 0
1.0/1.0
20
µA/−0.6 mA
I1a–I1d
Data Inputs from Source 1
1.0/1.0
20
µA/−0.6 mA
Za–Zd
3-STATE Inverting Data Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Output
Select
Data
Output
Enable
Input
Inputs
OE
SI0
I1
Z
H
XXX
Z
LH
X
L
H
LH
X
H
L
LLL
X
H
LL
H
X
L


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