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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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74F322 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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74F322 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
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2 / 6 page  www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shift- ing or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the 3-STATE output buffers and enables parallel loading. In the shift right mode a HIGH sig- nal on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 74F384 Twos Com- plement Multiplier. A HIGH signal on OE disables the 3- STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance Output State = LOW-to-HIGH Transition NC = No Change Note: I7–I0 = The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the I/O terminal. Note: D0, D1 = The level of the steady-state inputs to the serial multiplexer input. Note: O7–O0 = The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition. Note 1: When the OE input is HIGH all I/On terminals are at the high impedance state; sequential operation or clearing of the register is not affected. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL RE Register Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA S/P Serial (HIGH) or Parallel (LOW) Mode Control Input 1.0/1.0 20 µA/−0.6 mA SE Sign Extend Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA S Serial Data Select Input 1.0/2.0 20 µA/−1.2 mA D0, D1 Serial Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q0 Bi-State Serial Output 50/33.3 −1 mA/−20 mA I/O0–I/O7 Multiplexed Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA 3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Mode Inputs Outputs Q0 MR RE S/P SE SOE (Note 1) CP I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Clear L X X X X L X L L LLL LLL L L X X X X H X ZZZ ZZZ ZZ L Parallel H L L X X X I7 I6 I5 I4 I3 I2 I1 I0 I0 Load Shift H L H H L L D0 O7 O6 O5 O4 O3 O2 O1 O1 Right H L H H H L D1 O7 O6 O5 O4 O3 O2 O1 O1 Sign H L H L X L O7 O7 O6 O5 O4 O3 O2 O1 O1 Extend Hold H H X X X L NC NC NC NC NC NC NC NC NC |
유사한 부품 번호 - 74F322 |
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유사한 설명 - 74F322 |
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