전자부품 데이터시트 검색엔진 |
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74FR900 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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74FR900 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Functional Description The 74FR900 allows 9-bit data to be transferred from any of three 9-bit I/O ports to either of the two remaining I/O ports. The device employs latches in all paths for either transparent or synchronous operation. Readback capability from any port to itself is also possible. Data transfer within the 74FR900 is controlled through use of the select (S0 and S1) and output-enable (OEA, OEB and OEC) inputs as described in Table 1. Additional control is available by use of the latch-enable inputs (LEAC, LECA, LEBC, LECB) allowing either synchronous or transparent transfers (see Table 2). Table 1 indicates several readback conditions. By latching data on a given port and initiating the readback control configuration, previous data may be read for system verification or diagnostics. This mode may be useful in implementing system diagnostics. Data at the port to be readback must be latched prior to enabling the outputs on that port. If this is not done, a closed data loop will result causing possible data integrity problems. Note that the A and B ports allow readback with- out affecting any other port. Port C, however, requires inter- ruption of either port A or B to complete its readback path. PINV controls inversion of the C8 bit. A low on PINV allows C8 data to pass unaltered. A high causes inversion of the data. See Table 3. This feature allows forcing of parity errors for use in system diagnostics. This is particularly helpful in 486 processor designs as the 486 does not pro- vide odd/even parity selection internally. TABLE 1. Datapath Control Note 1: Readback operation in latched mode only. Transparent operation could result in unpredictable results. TABLE 2. Latch-Enable Control TABLE 3. PINV Control L = LOW Voltage H = HIGH Voltage Level Q0 = Output state prior to LExx LOW-to-HIGH transition Logic Diagram Inputs Function S0 S1 OEA OEB OEC L X H L L Port A to Port C L L H H H Port A to Port B L O H H L Port A to B +C H L L L H Port B to Port A H X H L L Port B to Port C H O L L L Port B to A +C X H L L H Port C to Port A X H H H H Port C to Port B X H L H H Port C to A +B X X H L H Outputs Disabled L L L X X (Readback to A) (Note 1) L H L X L (Readback to A or C) (Note 1) H L X H X (Readback to B) (Note 1) H H X H L (Readback to B or C) (Note 1) LExx Input Output LL L LH H HX Q0 PINV C8 A8 or B8 LL L LH H HL H HH L |
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