74LCX112 datasheet(4/9 Pages) FAIRCHILD

부품명	74LCX112

상세설명	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs

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AC Electrical Characteristics

Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH).

Dynamic Switching Characteristics

Capacitance

Symbol

Parameters

TA = 40°C to 85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V

VCC = 2.7V

VCC = 2.5V ± 0.2V

CL=50 pF

CL = 50 pF

CL=30 pF

Min

Max

Min

Max

Min

Max

fMAX

Maximum Clock Frequency

150

MHz

tPHL

Propagation Delay

1.5

7.5

1.5

8.0

1.5

9.0

ns

tPLH

CPn to Qn or Qn

1.57.5

1.58.0

1.59.0

tPHL

Propagation Delay

1.5

7.0

1.5

8.0

1.5

8.4

ns

tPLH

CDn or SDn to Qn or Qn

1.57.0

1.78.0

1.58.4

tS

Setup Time

2.5

4.0

ns

tH

Hold Time

1.5

2.0

ns

tW

Pulse Width CP

3.3

4.0

ns

tW

Pulse Width (CD, SD)

3.3

4.0

ns

tREC

Recovery Time

2.0

2.5

4.5

ns

tOSHL

Output to Output Skew

1.0

ns

tOSLH

(Note 4)

1.0

Symbol

Parameter

Conditions

VCC

TA = 25°C

Units

(V)

Typical

VOLP

Quiet Output Dynamic Peak VOL

CL = 50 pF, VIH = 3.3V, VIL = 0V

3.3

0.8

V

CL = 30 pF, VIH = 2.5V, VIL = 0V

2.5

0.6

VOLV

Quiet Output Dynamic Valley VOL

CL = 50 pF, VIH = 3.3V, VIL = 0V

3.3

−0.8

V

CL = 30 pF, VIH = 2.5V, VIL = 0V

2.5

−0.6

Symbol

Parameter

Conditions

Typical

Units

CIN

Input Capacitance

VCC = Open, VI = 0V or VCC

7pF

COUT

Output Capacitance

VCC = 3.3V, VI = 0V or VCC

8pF

CPD

Power Dissipation Capacitance

VCC = 3.3V, VI = 0V or VCC, f = 10 MHz

25

pF

유사한 부품 번호 - 74LCX112

제조업체	부품명	데이터시트	상세설명
Fairchild Semiconductor	74LCX112	102Kb / 9P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
ON Semiconductor	74LCX112	205Kb / 11P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs Revised February 2001
	74LCX112M	205Kb / 11P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs Revised February 2001
	74LCX112MTC	205Kb / 11P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs Revised February 2001
Fairchild Semiconductor	74LCX112MTCX	102Kb / 9P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs

More results

유사한 설명 - 74LCX112

제조업체	부품명	데이터시트	상세설명
ON Semiconductor	74LCX112	205Kb / 11P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs Revised February 2001
Fairchild Semiconductor	74LCX112MTCX	102Kb / 9P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
NXP Semiconductors	74ALS112A	92Kb / 10P	Dual J-K negative edge-triggered flip-flop 1991 Feb 08
Texas Instruments	SN74F112NSR	627Kb / 13P	[Old version datasheet] DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
NXP Semiconductors	74F112	83Kb / 10P	Dual J-K negative edge-triggered flip-flop 1990 Feb 09
Mitsubishi Electric Sem...	M74LS73AP	220Kb / 4P	DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET
Fairchild Semiconductor	74LCX74	89Kb / 11P	Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
ON Semiconductor	74LCX74	682Kb / 13P	Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs December 2013 Rev. 1.7.1
Unisonic Technologies	U74LCX74	175Kb / 7P	LOW VOLTAGE DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP WITH 5V TOLERANT INPUTS
Texas Instruments	74ACT11112	75Kb / 5P	[Old version datasheet] DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

More results

74LCX112 데이터시트(PDF) 4 Page - Fairchild Semiconductor

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유사한 부품 번호 - 74LCX112

유사한 설명 - 74LCX112

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