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74LVX4245QSCX 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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74LVX4245QSCX 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page © 2003 Fairchild Semiconductor Corporation DS011540 www.fairchildsemi.com January 1993 Revised September 2003 74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs General Description The LVX4245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 5V bus and a 3V bus in a mixed 3V/5V supply environment. The Transmit/ Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a high impedance condition. The A Port interfaces with the 5V bus; the B Port interfaces with the 3V bus. The LVX4245 is suitable for mixed voltage applications such as laptop computers using 3.3V CPU’s and 5V LCD displays. Features s Bidirectional interface between 5V and 3V buses s Control inputs compatible with TTL level s 5V data flow at A Port and 3V data flow at B Port s Outputs source/sink 24 mA at 5V bus; 12 mA at 3V bus s Guaranteed simultaneous switching noise level and dynamic threshold performance s Implements patented EMI reduction circuitry s Functionally compatible with the 74 series 245 Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Order Number Package Number Package Description 74LVX4245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX4245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74LVX4245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State |
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