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DM74ALS5245SJX 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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DM74ALS5245SJX 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2000 Fairchild Semiconductor Corporation DS009175 www.fairchildsemi.com October 1986 Revised February 2000 DM74ALS5245 Octal 3-STATE Transceiver General Description This octal bus transceiver is designed for asynchronous two-way communication between data buses. The inputs include hysteresis which provides improved noise rejec- tion. Data is transmitted either from the A bus to the B bus or from the B bus to the A bus depending on the logic level of the direction control (DIR) input. The device can be dis- abled via the enable input (G) which causes the outputs to enter the high impedance mode so the buses are effec- tively isolated. Features s Input Hysteresis s Low output noise generation s High input noise immunity s Advanced oxide-isolated, ion implanted Schottky TTL process s Switching specification guaranteed over the full temper- ature and VCC range s PNP inputs to reduce input loading Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table L = LOW Logic Level H = HIGH Logic Level X = Don't Care (Either LOW or HIGH Logic Level) Order Number Package Number Package Description DM74ALS5245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS5245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS5245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Control Inputs Operation G DIR L L B Data to A Bus L H A Data to B Bus H X High Impedance |
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