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DM74AS286 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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DM74AS286 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2000 Fairchild Semiconductor Corporation DS006305 www.fairchildsemi.com October 1986 Revised April 2000 DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port General Description These universal, 9-bit parity generators/checkers utilize advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is eas- ily expanded by cascading. The DM74AS286 can be used to upgrade the performance of most systems utilizing the DM74AS280 parity generator/ checker. Although the DM74AS286 is implemented without expander inputs, the corresponding function is provided by the availability of an input pin XMIT. XMIT is a control line which makes parity error output active and parity an input port when HIGH; when LOW, parity error output is inactive and parity becomes an output port. In addition, parity I/O control circuitry contains a feature to keep the I/O port in the 3-STATE during power UP or DOWN to prevent bus glitches. Features s PNP inputs to reduce bus loading s Generates either odd or even parity for nine data lines s Inputs are buffered to lower the drive requirements s Can be used to upgrade existing systems using MSI parity circuits s Cascadable for n-bits s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s A parity I/O portable to drive bus Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table L = LOW Logic Level H = HIGH Logic Level N/A = Not Applicable Order Number Package Number Package Description DM74AS286M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74AS286N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Number of Inputs Parity I/O XMIT Parity Error Mode (A thru I) of that are HIGH Input Output Operation 0, 2, 4, 6, 8 N/A H L H Parity 1, 3, 5, 7, 9 N/A L L H Generator 0, 2, 4, 6, 8 H N/A H H Parity 0, 2, 4, 6, 8 L N/A H L Checker 1, 3, 5, 7, 9 H N/A H L Parity 1, 3, 5, 7, 9 L N/A H H Checker |
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