전자부품 데이터시트 검색엔진 |
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DM74S161 데이터시트(PDF) 6 Page - Fairchild Semiconductor |
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DM74S161 데이터시트(HTML) 6 Page - Fairchild Semiconductor |
6 / 7 page www.fairchildsemi.com 6 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Note 6: All typicals are at VCC = 5V, TA = 25°C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at VCC = 5V and TA = 25°C Note 8: Propagation delay for clearing is measured from clear input for the DM74S161 and from the clock input transition for the DM74S163. Symbol Parameter Conditions Min Typ Max Units (Note 6) VI Input Clamp Voltage VCC = Min, II = −18 mA −1.2 V VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max 0.5 V Output Voltage VIH = Min, VIL = Max II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA IIH LOW Level VCC = Max CLK, Data 50 µA Input Current VI = 2.7V Others −10 −200 IIL LOW Level VCC = Max Enable T −4mA Input Current VI = 0.5V Others −2 IOS Short Circuit Output Current VCC = Max (Note 7) −40 −100 mA ICC Supply Current VCC = Max 95 160 mA RL = 280Ω Symbol Parameter From (Input) CL = 15 pF CL = 50 pF Units To (Output) Min Max Min Max fMAX Maximum Clock Frequency 40 35 MHz tPLH Propagation Delay Time Clock to Ripple Carry 25 25 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to Ripple Carry 25 28 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Clock to Any Q 15 15 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to Any Q 15 18 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Enable T to Ripple Carry 15 18 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Enable T to Ripple Carry 15 18 ns HIGH-to-LOW Level Output tPHL Propagation Delay Time Clear to Any Q 20 24 ns HIGH-to-LOW Level Output (Note 8) |
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