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ISLA216P13 데이터시트(PDF) 8 Page - Intersil Corporation |
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ISLA216P13 데이터시트(HTML) 8 Page - Intersil Corporation |
8 / 25 page Application Note 1837 8 AN1837.0 May 3, 2013 Again, the green elements are optional and not populated. The non-populated elements connecting into C1005 would be the FDA VCM adjustment if desired. As delivered, C1005 simply decouples the ISL55210 VCM control pin which defaults internally to 1.2V on 3.3V supply. Not shown is a jumper on J2 from pin 2 to 3 to connect in the servo loop ADC VCM control path. The ISLA214P50 ADC uses an unbuffered sample and hold and will therefore sink a sample rate dependent common-mode current which will give a sample rate dependent voltage drop from the midpoint of resistors R1015 -- > R1018 and R2011, R2012. The servo loop is used primarily to counteract the sample-rate dependent voltage drop to deliver a fixed common- mode voltage to the ADC input pins across all sample clock rates. An alternate connection uses pin 2 to 1 on jumper J2 and populates R1019 to provide a fixed Thevenin source for the ADC VCM control. This provides a simpler solution when the design is known to be a fixed clock rate design. Numerous options exist for providing this ADC input VCM voltage for different designs. The two offered on this board, along with several others, are detailed in this article: “Advantages to Precise Input Common Mode Voltage Control to High Performance High Speed ADC’s” http://www.edn.com/design/analog/4389814/Advantages-to- precise-input-common-mode-voltage-control-to-high- performance-high-speed-ADCs?page=0 The differential signal at the outputs of the ISL55210 proceeds from left to right in Figure 8 through the 40.2Ω resistors to a differential 5.6pF capacitor and then into the 1μF DC blocking capacitors. Those level shift the DC operating voltage from the FDA outputs to the required common mode voltage at the ADC inputs. The rest of the passive filter from there is pair of series 82nH inductors then into a parallel RC network comprised of the 4 resistor network feeding the differential to single ended sense path at the output of T4, an external 1pF differential capacitor and then the internal RC elements of the ADC. A final circuit element senses the average common mode voltage at the ADC inputs using the 2-20kΩ resistors and feeds that into a low frequency servo loop amplifier using the ISL28113 which then feeds a DC control voltage to the center of the 4-resistor string that acts to control the ADC common mode operating voltage to the reference voltage applied at the ISL28113 V+ input. Critical to understanding the response shape are the estimated internal ADC elements as shown in the simulation circuit for this interface in Figure 9 (this element numbering here does not follow the build schematic of Figure 8) At the far right the ADC is modeled as 2-clock rate dependent current sources (1.3mA here for the 500MSPS case) with an internal lumped element 16pF in parallel with 200Ω. The probes show the DC operating voltages where the 2.22V at the ISL28113 outputs gets back to the targeted 0.96V at the ADC inputs as those Icm currents pull down through the DC impedances from the output of the ISL28113. The internal ADC elements combine with the external RC elements to give the simulated frequency response shape from the ISL55210 outputs to the ADC inputs shown in Figure 10. This slight peaking is intended to equalize some of the rolloff up to the FDA outputs but then bandlimit quickly above 100MHz. The VTEST of Figure 8 provides an easy means to verify the frequency response shape from the board input to the ADC. The 4 resistor network feeding T4 in Figure 8 shows a about a 25Ω source to each leg of the 1:1 transformer while its total impedance across the signal path is part of the filter design. This path will have considerable insertion loss (≈-31.8dB) but an accurate replica of the response shape as shown for 2 boards measured in Figure 11. FIGURE 9. SIMULATION CIRCUIT FOR THE INTERSTAGE FILTER AND VCM SERVO LOOP FIGURE 10. TARGETED RESPONSE SHAPE IN THE INTERSTAGE FILTER TO THE ADC -6.0 -5/5 -5.0 -4.5 -4.0 -3.0 20M 60M 80M 100M 150M FREQUENCY (Hz) -3.5 40M -2.5 |
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