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AD7416ARZ-REEL7 데이터시트(PDF) 8 Page - Analog Devices |
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AD7416ARZ-REEL7 데이터시트(HTML) 8 Page - Analog Devices |
8 / 24 page AD7416/AD7417/AD7418 Rev. I | Page 8 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 SDA 2 SCL 3 OTI 4 NC 16 CONVST 15 VDD 14 A0 13 REFIN 5 A1 12 GND 6 A2 11 AIN1 7 AIN4 10 AIN2 8 AIN3 9 NC = NO CONNECT AD7417 TOP VIEW (Not to Scale) Figure 6. AD7417 Pin Configuration (SOIC/TSSOP) Table 4. AD7417 Pin Function Descriptions Pin No. Mnemonic Description 1, 16 NC No Connection. Do not connect anything to this pin. 2 SDA Digital I/O. Serial bus bidirectional data. Push-pull output. 3 SCL Digital Input. Serial bus clock. 4 OTI This pin is a logic output. The overtemperature indicator (OTI) is set if the result of a conversion on Channel 0 (temperature sensor) is greater than an 8-bit word in the TOTI setpoint register. The signal is reset at the end of a serial read operation. Open-drain output. 5 REFIN Reference Input. An external 2.5 V reference can be connected to the AD7417 at this pin. To enable the on-chip reference, the REFIN pin should be tied to GND. If an external reference is connected to the AD7417, the internal reference shuts down. 6 GND Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry. 7 to 10 AIN1 to AIN4 Analog Input Channels. The AD7417 has four analog input channels. The input channels are single-ended with respect to GND. The input channels can convert voltage signals in the range of 0 V to VREF. A channel is selected by writing to the configuration register of the AD7417. 11 A2 Digital Input. This is the highest programmable bit of the serial bus address. 12 A1 Digital Input. This is the middle programmable bit of the serial bus address. 13 A0 Digital Input. This is the lowest programmable bit of the serial bus address. 14 VDD Positive Supply Voltage, 2.7 V to 5.5 V. 15 CONVST Logic Input Signal. Convert start signal. The rising edge of this signal fully powers up the part. The power-up time for the part is 4 μs. If the CONVST pulse is greater than 4 μs, the falling edge of CONVST places the track-and-hold mode into hold mode and initiates a conversion. If the pulse is less than 4 μs, an internal timer ensures that the track-and-hold does not go into hold, and conversion is not initiated until the power-up time has elapsed. The track-and-hold goes into track mode again at the end of conversion (see the section). Operating Modes |
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