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ADV7180WBST48Z 데이터시트(PDF) 10 Page - Analog Devices

부품명 ADV7180WBST48Z
상세설명  10-Bit, 4횞 Oversampling SDTV Video Decoder
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ADV7180
Data Sheet
Rev. G | Page 10 of 120
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 5.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
28.6363
MHz
Frequency Stability
±50
ppm
I2C PORT
SCLK Frequency
400
kHz
SCLK Minimum Pulse Width High
t1
0.6
µs
SCLK Minimum Pulse Width Low
t2
1.3
µs
Hold Time (Start Condition)
t3
0.6
µs
Setup Time (Start Condition)
t4
0.6
µs
SDA Setup Time
t5
100
ns
SCLK and SDA Rise Times
t6
300
ns
SCLK and SDA Fall Times
t7
300
ns
Setup Time for Stop Condition
t8
0.6
µs
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark Space Ratio
t9:t10
45:55
55:45
% duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
t11
Negative clock edge to start of valid data
(tACCESS = t10 − t11)
3.6
ns
Data Output Transitional Time
t12
End of valid data to negative clock edge
(tHOLD = t9 + t12)
2.4
ns
Timing Diagrams
SDATA
SCLK
t3
t5
t3
t4
t8
t6
t7
t2
t1
Figure 6. I2C Timing
OUTPUT LLC
OUTPUTS P0 TO P15, VS,
HS, FIELD,
SFL
t9
t10
t11
t12
Figure 7. Pixel Port and Control Output Timing


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