© 2001 Fairchild Semiconductor Corporation

DS500508

www.fairchildsemi.com

August 2001

Revised December 2001

FIN1032

3.3V LVDS 4-Bit High Speed Differential Receiver

General Description

This quad receiver is designed for high speed interconnect

utilizing Low Voltage Differential Signaling (LVDS) technol-

ogy. The receiver translates LVDS levels, with a typical dif-

ferential input threshold of 100mV, to LVTTL signal levels.

LVDS provides low EMI at ultra low power dissipation even

at high frequencies. This device is ideal for high speed

transfer of clock and data.

The FIN1032 can be paired with its companion driver, the

FIN1031, or any other Fairchild LVDS driver.

Features

s Greater than 400Mbs data rate

s 3.3V power supply operation

s 0.4ns maximum differential pulse skew

s 2.5ns maximum propagation delay

s Low power dissipation

s Power OFF protection

s Fail safe protection for open-circuit, shorted and termi-

nated conditions

s Meets or exceeds the TIA/EIA-644 LVDS standard

s Pin compatible with equivalent RS-422 and LVPECL

devices

s 16-Lead SOIC and TSSOP packages save space

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Function Table

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Don’t Care

Z

= High Impedance

Fail Safe

= Open, Shorted, Terminated

Connection Diagram

Pin Descriptions

Order Number

Package Number

Package Description

FIN1032M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

FIN1032MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Inputs

Outputs

EN

EN

HX

H

L

H

HX

L

H

L

H

X

Fail Safe Condition

H

XL

H

L

H

XL

L

H

L

X

L

Fail Safe Condition

H

LH

X

Z

Pin Name

Description

LVTTL Data Outputs

Non-Inverting LVDS Inputs

Inverting LVDS Inputs

EN

Driver Enable Pin

EN

Inverting Driver Enable Pin

Power Supply

GND

Ground