전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

CDCM7005RGZR 데이터시트(PDF) 8 Page - Texas Instruments

Click here to check the latest version.
부품명 CDCM7005RGZR
상세설명  3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
Download  45 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

CDCM7005RGZR 데이터시트(HTML) 8 Page - Texas Instruments

Back Button CDCM7005RGZR Datasheet HTML 4Page - Texas Instruments CDCM7005RGZR Datasheet HTML 5Page - Texas Instruments CDCM7005RGZR Datasheet HTML 6Page - Texas Instruments CDCM7005RGZR Datasheet HTML 7Page - Texas Instruments CDCM7005RGZR Datasheet HTML 8Page - Texas Instruments CDCM7005RGZR Datasheet HTML 9Page - Texas Instruments CDCM7005RGZR Datasheet HTML 10Page - Texas Instruments CDCM7005RGZR Datasheet HTML 11Page - Texas Instruments CDCM7005RGZR Datasheet HTML 12Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 45 page
background image
CDCM7005
SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013
www.ti.com
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS
Output frequency, see (1), (2), Figure 6,
Load = 5 pF to GND, 1 k
Ω to VCC, 1 kΩ
fclk
250
MHz
and Figure 7
to GND
VIK
LVCMOS input clamp voltage
VCC = 3 V, II = –18 mA
–1.2
V
LVCMOS input current for CTRL_LE,
II
VI = 0 V or VCC, VCC = 3.6 V
±5
µA
CTRL_CLK, CTRL_DATA
LVCMOS input current for PD, RESET,
IIH
HOLD, REF_SEL, PRI_REF,
VI = VCC, VCC = 3.6 V
5
µA
SEC_REF, (see (3))
LVCMOS input current for PD, RESET,
IIL
HOLD, REF_SEL, PRI_REF,
VI = 0 V, VCC = 3.6 V
–15
–35
µA
SEC_REF, (see (3))
VCC = min to max,
VCC–0.1
IOH = –100 μA
High-level output voltage for LVCMOS
VOH
V
outputs
VCC = 3 V, IOH = –6 mA
2.4
VCC = 3 V, IOH = –12 mA
2
VCC = min to max,
0.1
IOL = 100 μA
Low-level output voltage for LVCMOS
VOL
V
outputs
VCC = 3 V, IOL = 6 mA
0.5
VCC = 3 V, IOL = 12 mA
0.8
IOH
High-level output current
VCC = 3.3 V, VO = 1.65 V
–30
mA
IOL
Low-level output current
VCC = 3.3 V, VO = 1.65 V
33
mA
VREF_IN = VCC/2, Y = VCC/2,
tpho
Phase offset (REF_IN to Y output)(4)
1.8
ns
see Figure 11, Load = 10 pF
tsk(p)
LVCMOS pulse skew, see Figure 10
Crosspoint to VCC/2 load, see Figure 12
150
ps
tpd(LH)
Crosspoint to VCC/2,
Propagation delay from VCXO_IN to
Load = 10 pF, see Figure 12 (PLL
2
2.5
3
ns
Yx, see Figure 10
tpd(HL)
bypass mode)
All outputs have the same divider ratio
55
LVCMOS single-ended output skew,
tsk(o)
ps
see (5) and Figure 10
Outputs have different divider ratios
70
Duty cycle
LVCMOS
VCC/2 to VCC/2
49%
51%
20% to 80% of swing (load
tslew-rate
Output rise/fall slew rate
2.4
3.5
V/ns
see Figure 12)
LVPECL
fclk
Output frequency, see (6) and Figure 5
Load, see Figure 13
0
1500
MHz
II
LVPECL input current
VI = 0 V or VCC
±20
µA
VOH
LVPECL high-level output voltage
Load, See Figure 13
VCC–1.18
VCC–0.81
V
VOL
LVPECL low-level output voltage
Load, See Figure 13
VCC–2
VCC–1.55
V
|VOD|
Differential output voltage
See Figure 9 and load, see Figure 13
500
mV
VREF_IN = VCC/2 to cross point of Y,
tpho
Phase offset (REF_IN to Y output)(5)
–200
100
ps
see Figure 11
tpd(LH)
Propagation delay time, VCXO_IN to
Cross point-to-cross point, load
340
490
640
ps
Yx, see Figure 10
see Figure 13
tpd(HL)
Cross point-to-cross point, load
tsk(p)
LVPECL pulse skew, see Figure 10
10
ps
see Figure 13
(1)
fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA
package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4).
(2)
Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output
signal swing may no longer meet the output specification.
(3)
These inputs have an internal 150-k
Ω pullup resistor.
(4)
This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M
and VCXO delay N).
(5)
The tsk(o) specification is only valid for equal loading of all outputs.
(6)
Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output
signal swing may no longer meet the output specification.
8
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links :CDCM7005


유사한 부품 번호 - CDCM7005RGZR

제조업체부품명데이터시트상세설명
logo
Texas Instruments
CDCM7005RGZR TI-CDCM7005RGZR Datasheet
1Mb / 40P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
CDCM7005RGZR TI1-CDCM7005RGZR Datasheet
3Mb / 52P
[Old version datasheet]   3.3-V High Performance Clock Synchronizer and Jitter Cleaner
CDCM7005RGZRG4 TI1-CDCM7005RGZRG4 Datasheet
3Mb / 52P
[Old version datasheet]   3.3-V High Performance Clock Synchronizer and Jitter Cleaner
More results

유사한 설명 - CDCM7005RGZR

제조업체부품명데이터시트상세설명
logo
Texas Instruments
CDCM7005 TI-CDCM7005 Datasheet
1Mb / 40P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
CDCM7005 TI1-CDCM7005_15 Datasheet
3Mb / 52P
[Old version datasheet]   3.3-V High Performance Clock Synchronizer and Jitter Cleaner
CDCM7005-SP TI1-CDCM7005-SP Datasheet
570Kb / 41P
[Old version datasheet]   3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND JITTER CLEANER
CDC7005RGZT TI-CDC7005RGZT Datasheet
1Mb / 34P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER
CDC7005 TI-CDC7005 Datasheet
397Kb / 29P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
CDCM7005-SP TI1-CDCM7005-SP_16 Datasheet
1Mb / 49P
[Old version datasheet]   CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner
CDCE72010 TI-CDCE72010 Datasheet
1Mb / 70P
[Old version datasheet]   Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010 TI-CDCE72010_09 Datasheet
1Mb / 73P
[Old version datasheet]   Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
logo
Analog Devices
AD9523 AD-AD9523 Datasheet
1,011Kb / 60P
   Jitter Cleaner and Clock Generator
AD9524 AD-AD9524_15 Datasheet
973Kb / 56P
   Jitter Cleaner and Clock Generator
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com