전자부품 데이터시트 검색엔진 |
|
AD9959BCPZ 데이터시트(PDF) 9 Page - Analog Devices |
|
AD9959BCPZ 데이터시트(HTML) 9 Page - Analog Devices |
9 / 44 page AD9959 Rev. B | Page 9 of 44 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR NC = NO CONNECT 1 SYNC_IN 2 SYNC_OUT 3 MASTER_RESET 4 PWR_DWN_CTL 5 AVDD 6 AGND 7 AVDD 8 CH2_IOUT 9 CH2_IOUT 10 AGND 11 AVDD 12 AGND 13 CH3_IOUT 14 CH3_IOUT 35 CH1_IOUT 36 CH1_IOUT 37 AVDD 38 AGND 39 AVDD 40 P0 41 P1 42 P2 34 AGND 33 AVDD 32 AGND 31 AVDD 30 CH0_IOUT 29 CH0_IOUT TOP VIEW (Not to Scale) AD9959 NOTES 1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND. 2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V. Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic I/O1 Description 1 SYNC_IN I Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of the master AD9959 device. 2 SYNC_OUT O Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the slave AD9959 devices. 3 MASTER_RESET I Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal registers to their default state, as described in the Register Maps and Bit Descriptions section. 4 PWR_DWN_CTL I External Power-Down Control. 5, 7, 11, 15, 19, 21, 26, 31, 33, 37, 39 AVDD I Analog Power Supply Pins (1.8 V). 6, 10, 12, 16, 18, 20, 25, 28, 32, 34, 38 AGND I Analog Ground Pins. 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 8 CH2_IOUT O True DAC Output. Terminates into AVDD. 9 CH2_IOUT O Complementary DAC Output. Terminates into AVDD. 13 CH3_IOUT O True DAC Output. Terminates into AVDD. 14 CH3_IOUT O Complementary DAC Output. Terminates into AVDD. 17 DAC_RSET I Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is connected from Pin 17 to AGND. 22 REF_CLK I Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this pin should be decoupled to AVDD or AGND with a 0.1 μF capacitor. 23 REF_CLK I Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. See the Modes of Operation section for the reference clock configuration. |
유사한 부품 번호 - AD9959BCPZ |
|
유사한 설명 - AD9959BCPZ |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |