FM28V102-TG datasheet(8/16 Pages) CYPRESS

부품명	FM28V102-TG

상세설명	1Mbit (64Kx16)F-RAM Memory

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제조업체	CYPRESS [Cypress Semiconductor]

홈페이지	http://www.cypress.com

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8 / 16 page

FM28V102 - 64Kx16 F-RAM

Document Number: 001-86601 Rev. **

Page 8 of 16

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Symbol

Description

Ratings

VDD

Power Supply Voltage with respect to VSS

-1.0V to +4.5V

VIN

Voltage on any signal pin with respect to VSS

-1.0V to +4.5V and

VIN < VDD+1V

TSTG

Storage Temperature

-55 C to +125 C

TLEAD

Lead Temperature (Soldering, 10 seconds)

260 C

VESD

Electrostatic Discharge Voltage

- Human Body Model (AEC-Q100-002 Rev. E)

- Charged Device Model (AEC-Q100-011 Rev. B)

- Machine Model (AEC-Q100-003 Rev. E)

TBD

Package Moisture Sensitivity Level

MSL-3

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating

only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this

specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.0V to 3.6V unless otherwise specified)

Symbol

Parameter

Min

Typ

Max

Units

Notes

VDD

Power Supply

2.0

3.3

3.6

V

IDD

VDD Supply Current

7

12

mA

1

ISB

Standby Current

@

TA = 25°C

@

TA = 85°C

120

-

150

250

A

2

IZZ

Sleep Mode Current

@ TA = 25°C

@ TA = 85°C

3

-

5

8

A

3

ILI

Input Leakage Current

1

A

4

ILO

Output Leakage Current

1

A

4

VIH1

Input High Voltage (VDD=2.7V to 3.6V)

2.2

VDD + 0.3

V

VIH2

Input High Voltage (VDD=2.0V to 2.7V)

0.7*VDD

-

V

VIL1

Input Low Voltage (VDD=2.7V to 3.6V)

-0.3

0.8

V

VIL2

Input Low Voltage (VDD=2.0V to 2.7V)

-0.3

0.3*VDD

V

VOH1

Output High Voltage (IOH = -1 mA, VDD>2.7V)

2.4

V

VOH2

Output High Voltage (IOH = -100 A)

VDD-0.2

V

VOL1

Output Low Voltage (IOL = 2 mA, VDD>2.7V)

0.4

V

VOL2

Output Low Voltage (IOL = 150 A)

0.2

V

RIN

Address Input Resistance (/ZZ)

For VIN = VIH (min)

For VIN = VIL (max)

40

1

K

M

5

Notes

1.

VDD = 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded.

2.

VDD = 3.6V, /CE at VDD, All other pins are static and at CMOS levels (0.2V or VDD-0.2V), /ZZ is high.

3.

VDD = 3.6V, /ZZ is low, all other inputs at CMOS levels (0.2V or VDD-0.2V).

4.

VIN, VOUT between VDD and VSS.

5.

The input pull-up circuit is stronger (>40K ) when the input voltage is above VIH and weak (>1M ) when the input

voltage is below VIL.

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