전자부품 데이터시트 검색엔진 |
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FM25040B 데이터시트(PDF) 2 Page - Cypress Semiconductor |
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FM25040B 데이터시트(HTML) 2 Page - Cypress Semiconductor |
2 / 14 page FM25040B - 4Kb 5V SPI F-RAM Document Number: 001-86145 Rev. *A Page 2 of 14 Instruction Decode Clock Generator Control Logic Write Protect Instruction Register Address Register Counter 64 x 64 FRAM Array 9 Data I/O Register 8 Nonvolatile Status Register 2 WP CS HOLD SCK SO SI Figure 1. Block Diagram Pin Descriptions Pin Name I/O Description /CS Input Chip Select. This active-low input activates the device. When high, the device enters low- power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. SCK Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 20 MHz and may be interrupted at any time. /HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. /WP Input Write Protect: This active-low pin prevents all write operations, including those to the status register. If high, write access is determined by the other write protection features, as controlled through the status register. A complete explanation of write protection is provided on page 6. SI Input Serial Input: All input data is driven to this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. SO Output Serial Output: SO is the data output pin. It is driven actively during a read and remains tri- state at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * SO can be connected to SI for a single pin data interface since the part communicates in half-duplex fashion. VDD Supply Supply Voltage: 5V VSS Supply Ground |
유사한 부품 번호 - FM25040B_13 |
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유사한 설명 - FM25040B_13 |
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