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FAN3988IL6X-F113 데이터시트(PDF) 5 Page - Fairchild Semiconductor

부품명 FAN3988IL6X-F113
상세설명  PFC/ PWM Controller Combination
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4800AU/CU • Rev. 1.0.0
5
Pin Configuration
Figure 6. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
IEA
Output of PFC Current Amplifier. The signal from this pin is compared with an internal
sawtooth to determine the pulse width for the PFC gate drive.
2
IAC
Input AC Current. For normal operation, this input provides a current reference for the
multiplier. The suggested maximum IAC is 65µA.
3
ISENSE
PFC Current Sense. The inverting input of the PFC current amplifier and the output of
multiplier and PFC ILIMIT comparator.
4
VRMS
Line-Voltage Detection. The pin is used for the PFC multiplier.
5
SS
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10µA constant
current source. The voltage on FBPWM is clamped by SS during startup. If a protection
condition occurs and/or PWM is disabled, the SS pin is quickly discharged.
6
FBPWM
PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.
7
RT/CT
Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
8
RAMP
PWM RAMP Input. In Current Mode, this pin functions as the current-sense input. In Voltage
Mode, it is the feed-forward sense input from PFC output 380V (feed-forward ramp).
9
ILIMIT
Peak Current Limit Setting for PWM. The peak current limit setting for PWM.
10
GND
Ground
11
OPWM
PWM Gate Drive. The totem-pole output drive for the PWM MOSFET. This pin is internally
clamped under 19V to protect the MOSFET.
12
OPFC
PFC Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped
under 15V to protect the MOSFET.
13
VDD
Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and
9.3V, respectively. The operating current is lower than 10mA.
14
VREF
Reference Voltage. Buffered output for the internal 7.5V reference.
15
FBPFC
Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input
of PFC error amplifier. This pin is connected to the PFC output through a divider network.
16
VEA
Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.
A compensation network is connected between this pin and ground.


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