CD74HC297E datasheet(2/15 Pages) TI1

부품명	CD74HC297E

상세설명	High-Speed CMOS Logic Digital Phase-Locked Loop

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The phase detector generates an error signal waveform that,

at zero phase error, is a 50% duty factor square wave. At the

limits of linear operation, the phase detector output will be

either HIGH or LOW all of the time depending on the direction

of the phase error (

φIN - φOUT). Within these limits the phase

detector output varies linearly with the input phase error

according to the gain Kd, which is expressed in terms of

phase detector output per cycle or phase error. The phase

detector output can be defined to vary between

±1 according

to the relation:

The output of the phase detector will be Kdφe, where the

phase error

φe = φIN - φOUT.

EXCLUSIVE-OR phase detectors (XORPD) and edge-con-

trolled phase detectors (ECPD) are commonly used digital

types. The ECPD is more complex than the XORPD logic

function but can be described generally as a circuit that

changes states on one of the transitions of its inputs. The gain

(Kd) for an XORPD is 4 because its output remains HIGH

(XORPDOUT = 1) for a phase error of one quarter cycle.

Similarly, Kd for the ECPD is 2 since its output remains HIGH

for a phase error of one half cycle. The type of phase detector

will determine the zero-phase-error point, i.e., the phase sep-

aration of the phase detector inputs for a

φe defined to be

zero. For the basic DPLL system of Figure 3,

φe = 0 when the

phase detector output is a square wave.

The XORPD inputs are one quarter cycle out-of-phase for

zero phase error. For the ECPD,

φe = 0 when the inputs are

one half cycle out of phase.

The phase detector output controls the up/down input to the

K-counter. The counter is clocked by input frequency Mfc

which is a multiple M of the loop center frequency fc. When

the K-counter recycles up, it generates a carry pulse. Recy-

cling while counting down generates a borrow pulse. If the

carry and the borrow outputs are conceptually combined into

one output that is positive for a carry and negative for a bor-

row, and if the K-counter is considered as a frequency divider

with the ratio Mfc/K, the output of the K-counter will equal the

input frequency multiplied by the division ratio. Thus the out-

put from the K-counter is (KdφeMfc)/K.

The carry and borrow pulses go to the increment/decrement

(I/D) circuit which, in the absence of any carry or borrow

pulses has an output that is one half of the input clock (I/DCP).

The input clock is just a multiple, 2N, of the loop center fre-

quency. In response to a carry of borrow pulse, the I/D circuit

will either add or delete a pulse at I/DOUT. Thus the output of

the I/D circuit will be Nfc + (KdφeMfc)/2K.

The output of the N-counter (or the output of the phase-

locked-loop) is thus: fo = fc + (KdφeMfc)/2KN.

If this result is compared to the equation for a first-order ana-

log phase-locked-loop, the digital equivalent of the gain of the

VCO is just Mfc/2KN or fc/K for M = 2N.

Thus, the simple first-order phase-locked-loop with an adjust-

able K-counter is the equivalent of an analog phase-locked-

loop with a programmable VCO gain.

Functional Diagram

phase detector output =

%HIGH - %LOW

100

--------------------------------------------

FUNCTION TABLE

EXCLUSIVE-OR PHASE DETECTOR

φA1

φB

XORPD OUT

LL

L

LH

H

HL

H

HH

L

FUNCTION TABLE

EDGE-CONTROLLED PHASE DETECTOR

φA2

φB

ECPD OUT

H or L

↓

H

↓

H or L

L

H or L

↑

No Change

↑

H or L

No Change

H = Steady-State High Level, L = Steady-State Low Level,

↑ = LOW

to HIGH

φ Transition, ↓ = HIGH to LOW φ Transition

K-COUNTER FUNCTION TABLE

(DIGITAL CONTROL)

DCBA

MODULO

(K)

LLLL

Inhibited

LLL

H

23

LL

H

L

24

LL

H

25

LHL

L

26

LHLH

27

LH

HL

28

L

HHH

29

H

LLL

210

HL

LH

211

HLHL

212

HLH

H

213

HH

L

214

HH

L

H

215

HHH

L

216

HHHH

217

MODULO-K

COUNTER

KCP

D/U

ENCTR

4

6

3

5

9

10

13

14 15

1

2

CARRY

BORROW

I/D

CKT

DCBA

I/DCP

φA

1

φB

φA

2

J

F/F

Q

K

7

11

12

I/DOUT

XORPDOUT

ECPDOUT

CD54HC297, CD74HC297, CD74HCT297

유사한 부품 번호 - CD74HC297E

제조업체	부품명	데이터시트	상세설명
Texas Instruments	CD74HC297E	251Kb / 15P	[Old version datasheet] High-Speed CMOS Logic Digital Phase-Locked Loop
Texas Instruments	CD74HC297EE4	251Kb / 15P	[Old version datasheet] High-Speed CMOS Logic Digital Phase-Locked Loop

More results

유사한 설명 - CD74HC297E

제조업체	부품명	데이터시트	상세설명
Texas Instruments	CD54HC297	251Kb / 15P	[Old version datasheet] High-Speed CMOS Logic Digital Phase-Locked Loop
	CD54HC297	243Kb / 14P	[Old version datasheet] High-Speed CMOS Logic Digital Phase-Locked Loop
	CD74HC297	97Kb / 11P	[Old version datasheet] High-Speed CMOS Logic Digital Phase-Locked-Loop
	SN74LV4046A	1Mb / 26P	[Old version datasheet] High-Speed CMOS Logic Phase-Locked Loop
	CD74HC4046A	316Kb / 28P	[Old version datasheet] High-Speed CMOS Logic Phase-Locked Loop with VCO
	SN74LV4046A	503Kb / 15P	[Old version datasheet] HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO
	CD54HC4046A	443Kb / 28P	[Old version datasheet] High-Speed CMOS Logic Phase-Locked Loop with VCO
	SN74LV4046A	536Kb / 15P	[Old version datasheet] HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO
	CD54HC4046A	505Kb / 32P	[Old version datasheet] High-Speed CMOS Logic Phase-Locked Loop with VCO
	SN74LV4046A	297Kb / 12P	[Old version datasheet] HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO

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CD74HC297E 데이터시트(PDF) 2 Page - Texas Instruments

CD74HC297E 데이터시트(HTML) 2 Page - Texas Instruments

유사한 부품 번호 - CD74HC297E

유사한 설명 - CD74HC297E

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