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Si5328-EVB 데이터시트(PDF) 10 Page - Silicon Laboratories |
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Si5328-EVB 데이터시트(HTML) 10 Page - Silicon Laboratories |
10 / 70 page Si5328 10 Rev. 1.0 Output Rise/Fall (20–80%) @ 312.5 MHz output CKOTRF LVPECL, LVDS or CML Output —230 350 ps Output Duty Cycle Uncertainty @ 808 MHz CKODC 100 Load Line-to-Line Measured at 50% Point (Not for CMOS) 45 — 55 % LVCMOS Input Pins Minimum Reset Pulse Width tRSTMN 1µs Reset to Microproces- sor Access Ready tREADY 10 ms Input Capacitance Cin —— 3 pF LVCMOS Output Pins Rise/Fall Times tRF CLOAD =20pf See Figure 2 —25 — ns LOSn Trigger Window LOSTRIG From last CKINn to Internal detection of LOSn N3 ≠ 1 —— 4.5 x N3 TCKIN Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Fold = Fnew Stable Xa/XB reference —10 — ms Device Skew Output Clock Skew tSKEW of CKOUTn to of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format PHASEOFFSET =0 CKOUT_ALWAYS_ON =1 SQ_ICAL =1 —— 100 ps Phase Change due to Temperature Variation tTEMP Max phase changes from – 40 to +85 °C, stable XAXB reference —300 500 ps Table 3. AC Characteristics (Continued) (VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for further details. 2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details. |
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