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ML4800CP 데이터시트(PDF) 10 Page - Fairchild Semiconductor |
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ML4800CP 데이터시트(HTML) 10 Page - Fairchild Semiconductor |
10 / 14 page ML4800 10 REV. 1.0.2 3/7/2001 FUNCTIONAL DESCRIPTION (Continued) Oscillator (RAMP 1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: (2) The dead time of the oscillator is derived from the following equation: (3) at VREF = 7.5V: The dead time of the oscillator may be determined using: (4) The dead time is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: (5) EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: Solving for RT x CT yields 1.96 x 10-4. Selecting standard components values, CT = 390pF, and RT = 51.1kΩ. The dead time of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT. PWM SECTION Pulse Width Modulator The PWM section of the ML4800 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltage-mode operation or certain specialized applications, RAMP 2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input would is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4800, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.45V. Once this voltage reaches 2.45V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP 2) When the PWM section is used in current mode, RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM’s output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25 µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: f tt OSC RAMP DEADTIME = + 1 tC R In V V RAMP T T REF REF =× × − − 125 375 . . tC R RAMP T T =× × 051 . t V mA CC DEADTIME T T =× = × 25 55 450 . . f t OSC RAMP = 1 fkHz t OSC RAMP == 100 1 |
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