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ML4812CP 데이터시트(PDF) 6 Page - Fairchild Semiconductor |
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ML4812CP 데이터시트(HTML) 6 Page - Fairchild Semiconductor |
6 / 16 page ML4812 6 REV. 1.0 10/10/2000 OUTPUT DRIVER STAGE The ML4812 output driver is a 1A peak output high speed totem pole circuit designed to quickly drive capacitive loads, such as power MOSFET gates. (Figure 3) ERROR AMPLIFIER The ML4812 error amplifier is a high open loop gain, wide bandwidth, amplifier.(Figures 4-5) GAIN MODULATOR The ML4812 gain modulator is of the current-input type to provide high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a dropping resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator. The output of the gain modulator is a current of the form: IOUT is proportional to ISINE ↔ IEA, where ISINE is the current in the dropping resistor, and IEA is a current proportional to FUNCTIONAL DESCRIPTION (Continued) Figure 5. Error Amplifier Open-Loop Gain and Phase vs Frequency Figure 7. Gain Modulator Linearity 5V EA– 4 3 – + 8V 0.5mA EA OUT Figure 4. Error Amplifier Configuration the output of the error amplifier. When the error amplifier is saturated high, the output of the gain modulator is approximately equal to the ISINE input current. The gain modulator output current is converted into the reference voltage for the PWM comparator through a resistor to ground on the gain modulator output. The gain modulator output is clamped to 5V to provide current limiting. Ramp compensation is accomplished by subtracting 1/2 of the current flowing out of RAMP COMP through a buffer transistor driven by CT which is set by an external resistor. UNDER VOLTAGE LOCKOUT On power-up the ML4812 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 10V, the UVLO condition is imposed. During the UVLO condition, the 5V VREF pin is “off”, making it usable as a “flag” for starting up a downstream PWM converter. 6 2 7 16 CT RAMP COMP GM OUT ISINE ERROR CURRENT 9V 5V IRAMP COMP ISINE × ERROR CURRENT – IRAMP COMP/2 Figure 6. Gain Modulator Block Diagram 500 400 300 200 100 0 SINE INPUT CURRENT (µA) 0 200 300 500 400 100 4.5 4.0 3.5 3.0 2.5 2.0 1.5 FREQUENCY (Hz) 10 1k 1M 100 10k 10M 100k 100 80 60 40 20 0 -20 0 -30 -60 -90 -120 -150 -180 GAIN PHASE |
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