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KA431DTF 데이터시트(PDF) 10 Page - Fairchild Semiconductor |
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KA431DTF 데이터시트(HTML) 10 Page - Fairchild Semiconductor |
10 / 11 page © 2004 Fairchild Semiconductor Corporation www.fairchildsemi.com KA431 / KA431A / KA431L Rev. 1.2.1 10 Physical Dimensions (Continued) Figure 19. 8-Lead, SOIC, JEDEC MS 0-12, 0.150 inch Narrow Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/M0/M08A.pdf. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-M08A_PSTS.pdf. 8° 0° SEE DETAIL A NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08Arev14 F) FAIRCHILD SEMICONDUCTOR. LAND PATTERN RECOMMENDATION SEATING PLANE C GAGE PLANE x 45° DETAIL A SCALE: 2:1 PIN ONE INDICATOR 4 8 1 B 5 A 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 MAX 0.25 0.19 0.36 0.50 0.25 R0.10 R0.10 0.90 0.40 (1.04) OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE 0.25 C B A 0.10 8-SOIC |
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