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SI8430BB-C-IS 데이터시트(PDF) 10 Page - Silicon Laboratories |
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SI8430BB-C-IS 데이터시트(HTML) 10 Page - Silicon Laboratories |
10 / 38 page Si8430/31/35 10 Rev. 1.5 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430Bx, Si8435Bx VDD1 VDD2 — — 2.7 3.0 4.1 4.2 mA Si8431Bx VDD1 VDD2 — — 3.1 3.2 4.3 4.5 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8430Bx, Si8435Bx VDD1 VDD2 — — 2.8 10.1 4.2 12.6 mA Si8431Bx VDD1 VDD2 — — 5.5 8.0 6.9 10.0 mA Timing Characteristics Si843xAx Maximum Data Rate 0— 1.0 Mbps Minimum Pulse Width —— 250 ns Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns Pulse Width Distortion |tPLH - tPHL| PWD See Figure 2 — — 25 ns Propagation Delay Skew2 tPSK(P-P) — — 40 ns Channel-Channel Skew tPSK — — 35 ns Table 4. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 25 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. |
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