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SI5330H-A00222-GM 데이터시트(PDF) 9 Page - Silicon Laboratories |
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SI5330H-A00222-GM 데이터시트(HTML) 9 Page - Silicon Laboratories |
9 / 20 page Si5330 Rev. 1.0 9 3. Functional Description The Si5330 is a low-jitter, low-skew fanout buffer optimized for high-performance PCB clock distribution applications. The device produces four differential or eight single-ended, low-jitter output clocks from a single input clock. The input can accept either a single-ended or a differential clock allowing the device to function as a clock level translator. 3.1. VDD and VDDO Supplies The core VDD and output VDDO supplies have separate and independent supply pins allowing the core supply to operate at a different voltage than the I/O voltage levels. The VDD supply powers the core functions of the device, which operates from 1.8, 2.5, or 3.3 V. Using a lower supply voltage helps minimize the device’s power consumption. The VDDO supply pins are used to set the output signal levels and must be set at a voltage level compatible with the output signal format. 3.2. Loss Of Signal Indicator (LOS) The input is monitored for a valid clock signal using an LOS circuit that monitors input clock edges and declares an LOS condition when signal edges are not detected over a 1 to 5 μs observation period. The LOS pin is asserted “low” when activity on the input clock pin is present. A “high” level on the LOS pin indicates a loss of signal (LOS). The LOS pin must be pulled to VDD as shown in Figure 2. Figure 2. LOS Indicator with External Pull-Up 3.3. Output Enable (OEB) The output enable (OEB) pin allows disabling or enabling of the outputs clocks (CLK0-CLK3). The output enable is logically controlled to ensure that no glitches or runt pulses are generated at the output as shown in Figure 3. Figure 3. OEB Glitchless Operation All outputs are enabled when the OEB pin is connected to ground or below the VIL voltage for this pin. Connecting the OEB pin to VDD or above the VIH level will disable the outputs. Both VIL and VIH are specified in Table 5. All outputs are forced to a logic “low” when disabled. The OEB pin is 3.3 V tolerant. 3.4. Input Signals The Si5330 can accept single-ended and differential input clocks. See “AN408: Termination Options for Any- Frequency, Any-Output Clock Generators and Clock Buffers—Si5338, Si5334, Si5330” for details on connecting a wide variety of signals to the Si5330 inputs. 3.5. Output Driver Formats The Si5330 supports single-ended output formats of CMOS, SSTL, and HSTL and differential formats of LVDS, LVPECL, and HCSL. It is normally required that the LVDS driver be dc-coupled to the 100 termination at the receiver end. If your application requires an ac- coupled 100 load, contact the applications team for advice. See AN408 for additional information on the terminations for these driver types. 3.6. Input and Output Terminations See AN408 for detailed information. 4. Ordering the Si5330 The Si5330 can be ordered to meet the requirements of the most commonly-used input and output signal types, such as CMOS, SSTL, HSTL, LVPECL, LVDS, and HSCL. See Figure 1, “Si5330 Functional Block Diagrams,” on page 2 and Table 11, “Order Numbers and Device Functionality,” on page 14 for specific ordering information. Si5330 Control LOS IN VDDO0 CLK0 VDDO1 CLK1 VDDO2 CLK2 VDDO3 CLK3 VDD 1k Valid Clock No Clock 0 1 IN CLKn OEB Enable Disable Disable Enable |
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