AD7801BRU datasheet(2/16 Pages) AD

부품명	AD7801BRU

상세설명	2.7 V to 5.5 V, Parallel Input, Voltage Output 8-Bit DAC

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2 / 16 page

–2–

REV. 0

AD7801–SPECIFICATIONS

(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 k

to VDD and GND.

All specifications TMIN to TMAX unless otherwise noted.)

Parameter

B Versions1

Units

Conditions/Comments

STATIC PERFORMANCE

Resolution

8

Bits

Relative Accuracy

2

±1

LSB max

Differential Nonlinearity

±1

LSB max

Guaranteed Monotonic

Zero-Code Error @ +25

°C

3

LSB typ

All Zeros Loaded to DAC Register

Full-Scale Error

–0.75

LSB typ

All Ones Loaded to DAC Register

Zero-Code Error Drift

100

µV/°C typ

Gain Error

3

±1

% FSR typ

DAC REFERENCE INPUT

REFIN Input Range

1 to VDD/2

V min/V max

REFIN Input Impedance

10

M

Ω typ

OUTPUT CHARACTERISTICS

Output Voltage Range

0 to VDD

V min/V max

Output Voltage Settling Time

2

µs max

Typically 1.2

µs

Slew Rate

7.5

V/

µs typ

Digital-to-Analog Glitch Impulse

1

nV-s typ

1 LSB Change Around Major Carry

Digital Feedthrough

0.2

nV-s typ

DC Output Impedance

40

Ω typ

Short Circuit Current

14

mA typ

Power Supply Rejection Ratio

4

0.0003

%/% max

∆V

DD = ± 10%

LOGIC INPUTS

Input Current

±10

µA max

VINL, Input Low Voltage

0.8

V max

VDD = +5 V

VINL, Input Low Voltage

0.6

V max

VDD = +3 V

VINH, Input High Voltage

2.4

V min

VDD = +5 V

VINH, Input High Voltage

2.1

V min

VDD = +3 V

Pin Capacitance

7

pF max

POWER REQUIREMENTS

VDD

2.7/5.5

V min/V max

IDD (Normal Mode)

DAC Active and Excluding Load Current

VDD = 3.3 V

VIH = VDD and VIL = GND

@ 25

°C

1.55

mA max

See Figure 6

TMIN to TMAX

1.75

mA max

VDD = 5.5 V

@ 25

°C

2.35

mA max

TMIN to TMAX

2.5

mA max

IDD (Power-Down)

@ 25

°C1

µA max

VIH = VDD and VIL = GND

TMIN to TMAX

2

µA max

See Figure 18

NOTES

1Temperature ranges are as follows: B Version: –40

°C to +105°C

2Relative Accuracy is calculated using a reduced code range of 15 to 245.

3Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.

4Guaranteed by characterization at product release, not production tested.

Specifications subject to change without notice.

Figure 1. Timing Diagram for Parallel Data Write

t1

t2

t4

t3

t5

t6

t7

t8

CS

WR

D7-D0

LDAC

CLR

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