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AD5246BKSZ10-RL7 데이터시트(PDF) 3 Page - Analog Devices |
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AD5246BKSZ10-RL7 데이터시트(HTML) 3 Page - Analog Devices |
3 / 16 page Data Sheet AD5246 Rev. C | Page 3 of 16 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 kΩ VERSION VDD = 5 V ± 10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB –1.5 ±0.1 +1.5 LSB Resistor Integral Nonlinearity2 R-INL RWB –4 ±0.75 +4 LSB Nominal Resistor Tolerance3 ∆RAB TA = 25°C –30 +30 % Resistance Temperature Coefficient (∆RAB/RAB)/∆T Wiper = no connect 45 ppm/°C RWB RWB Code = 0x00, VDD = 5 V 75 150 Ω Code = 0x00, VDD = 2.7 V 150 400 Ω RESISTOR TERMINALS Voltage Range4 VB, W GND VDD V Capacitance5 B CB f = 1 MHz, measured to GND, code = 0x40 45 pF Capacitance5 W CW f = 1 MHz, measured to GND, code = 0x40 60 pF Common-Mode Leakage ICM 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V 2.4 V Input Logic Low VIL VDD = 5 V 0.8 V Input Logic High VIH VDD = 3 V 2.1 V Input Logic Low VIL VDD = 3 V 0.6 V Input Current IIL VIN = 0 V or 5 V ±1 µA Input Capacitance5 CIL 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2.7 5.5 V Supply Current IDD VDD = 5.5 V; VIH = VDD or VIL = GND 3 7 µA VDD = 5 V; VIH = VDD or VIL = GND 2.5 5.2 µA VDD = 3.3 V; VIH = VDD or VIL = GND 0.9 2 µA Power Dissipation6 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 40 µW Power Supply Sensitivity PSSR VDD = +5 V ± 10%, code = midscale ±0.01 ±0.025 %/% DYNAMIC CHARACTERISTICS5, 7 Bandwidth –3 dB BW_5K RAB = 5 kΩ, code = 0x40 1.2 MHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 % VW Settling Time tS VA = 5 V, ±1 LSB error band 1 µs Resistor Noise Voltage Density eN_WB RWB = 2.5 kΩ, RS = 0 Ω 6 nV/√Hz 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design; not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 VDD = 5 V. |
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