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AD8582ARZ 데이터시트(PDF) 4 Page - Analog Devices |
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AD8582ARZ 데이터시트(HTML) 4 Page - Analog Devices |
4 / 8 page REV. 0 –4– AD8582 Table I. Control Logic Truth Table CS A /B LDA LDB RST MSB Input Register DAC Register L L HHHX Write to A Latched L HHHHX Write to B Latched LLL H H X Write to A A Transparent L H H L H X Write to B B Transparent H X L L H X Latched A & B Transparent H X ^ ^ H X Latched Latched XXXXL L Reset to Zero Scale Reset to Zero Scale XXXXL H Reset to Midscale Reset to Midscale H XXX^ X Latch Reset Value Latch Reset Value ^Denotes positive edge triggered. OPERATION The AD8582 is a complete, ready-to-use dual 12-bit digital-to- analog converter. Only one +5 V power supply is necessary for operation. It contains two voltage-switched, 12-bit, laser- trimmed digital-to-analog converters, a curvature-corrected bandgap reference, rail-to-rail output op amps, input registers, and DAC registers. The parallel data interface consists of twelve data bits, DB0–DB11, an address select pin A/B, two load strobe pins (LDA, LDB) and an active low CS strobe. In addi- tion an asynchronous RST pin will set all DAC register bits to zero causing the VOUT to become zero volts, or to midscale for trimming applications when the MSB pin is programmed to Logic 1. This function is useful for power on reset or system failure recovery to a known state. D/A CONVERTER SECTION The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt in- ternal bandgap voltage. It uses a laser trimmed R-2R ladder which is switched by N channel MOSFETs. The out- put voltage of the DAC has a constant resistance independent of digital input code. The DAC output (not available to the user) is internally connected to the rail-to-rail output op amp. AMPLIFIER SECTION The internal DAC’s output is buffered by a low power con- sumption precision amplifier. This low power amplifier contains a differential PNP pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zero- scale DAC output voltages. The rail-to-rail amplifier is config- ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an equivalent circuit schematic of the analog section. The op amp has a 16 µs typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the Typical Per- formances section of this data sheet. Figure 3. Equivalent Schematic of Analog Portion R1 R2 VOUT RAIL-TO-RAIL OUTPUT AMPLIFIER R BANDGAP REFERENCE VREF 2.5V 2R R 2R 2R SPDT N CH FET SWITCHES 2R AV = 4.095/2.5 = 1.638V/V VOLTAGE SWITCHED 12-BIT R-2R D/A CONVERTER BUFFER 2R OUTPUT SECTION The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P channel pull-up device that can sup- ply GND terminated loads, especially important at the –5% supply tolerance value of 4.75 volts. Figure 4. Equivalent Analog Output Circuit VDD VOUT AGND N-CH P-CH |
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