전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD7621 데이터시트(PDF) 9 Page - Analog Devices

부품명 AD7621
상세설명  16-Bit, 500 kSPS PulSAR Dual, 2-Channel, Simultaneous Sampling ADC
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD7621 데이터시트(HTML) 9 Page - Analog Devices

Back Button AD7621 Datasheet HTML 5Page - Analog Devices AD7621 Datasheet HTML 6Page - Analog Devices AD7621 Datasheet HTML 7Page - Analog Devices AD7621 Datasheet HTML 8Page - Analog Devices AD7621 Datasheet HTML 9Page - Analog Devices AD7621 Datasheet HTML 10Page - Analog Devices AD7621 Datasheet HTML 11Page - Analog Devices AD7621 Datasheet HTML 12Page - Analog Devices AD7621 Datasheet HTML 13Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 28 page
background image
AD7654
Rev. B | Page 9 of 28
Pin No.
Mnemonic
Type1
Description
15
D[6]
DI/O
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
or INVSCLK
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.
16
D[7]
DI/O
When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
or RDC/SDIN
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output
on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(5 V or 3 V).
19, 36
DVDD
P
Digital Power. Nominally at 5 V.
21
D[8]
DO
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel port data output bus.
or SDOUT
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7654 provides the two
conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled
by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
22
D[9]
DI/O
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends on the logic state of the INVSCLK pin.
23
D[10]
DO
When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.
or SYNC
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After
the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is
output, SYNC is pulsed HIGH.
24
D[11]
DO
When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus.
or RDERROR
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In Slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25 to 28
D[12:15]
DO
Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high
impedance.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two
conversions are complete and the data is latched into the on-chip shift register. The falling edge of
BUSY can be used as a data ready clock signal.
30
EOC
DO
End of Convert Output. Goes LOW at each channel conversion.
31
RD
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external serial clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7654. Current conversion if any is aborted. If not
used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.


유사한 부품 번호 - AD7621

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7621 AD-AD7621 Datasheet
818Kb / 32P
   16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC
REV. 0
AD7621 AD-AD7621 Datasheet
820Kb / 32P
   16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC
REV. 0
AD7621 AD-AD7621 Datasheet
868Kb / 32P
   14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC
REV. 0
AD7621 AD-AD7621 Datasheet
926Kb / 32P
   Ultralow Power, Low Distortion
REV. B
AD7621 AD-AD7621 Datasheet
619Kb / 32P
   16-Bit, 2 LSB INL, 3 MSPS PulSAR짰 ADC
REV. 0
More results

유사한 설명 - AD7621

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7654 AD-AD7654_15 Datasheet
520Kb / 27P
   16-Bit, 500 kSPS PulSAR Dual, 2-Channel, Simultaneous Sampling ADC
REV. C
AD7654 AD-AD7654_17 Datasheet
473Kb / 28P
   16-Bit, 500 kSPS PulSAR Dual, 2-Channel, Simultaneous Sampling ADC
AD7654ASTZ AD-AD7654ASTZ Datasheet
548Kb / 28P
   16-Bit, 500 kSPS PulSAR짰 Dual, 2-Channel, Simultaneous Sampling ADC
REV. B
AD7699 AD-AD7699 Datasheet
542Kb / 28P
   16-Bit, 8-Channel, 500 kSPS PulSAR ADC
REV. 0
AD7686 AD-AD7686 Datasheet
566Kb / 29P
   16-Bit, 500 kSPS PulSAR ADC in MSOP
AD7655 AD-AD7655_17 Datasheet
593Kb / 27P
   Low Cost, 4-Channel, 16-Bit, 500 kSPS PulSAR ADC
AD7656A AD-AD7656A_17 Datasheet
521Kb / 29P
   250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC
AD7656A AD-AD7656A Datasheet
498Kb / 28P
   250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC
AD7862ANZ-10 AD-AD7862ANZ-10 Datasheet
331Kb / 16P
   Simultaneous Sampling Dual 250 kSPS 12-Bit ADC
REV. 0
AD7862ARSZ-10 AD-AD7862ARSZ-10 Datasheet
417Kb / 16P
   Simultaneous Sampling Dual 250 kSPS 12-Bit ADC
REV. 0
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com