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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TLC2574IDW 데이터시트(PDF) 1 Page - Texas Instruments |
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TLC2574IDW 데이터시트(HTML) 1 Page - Texas Instruments |
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1 / 49 page  1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SCLK FS SDI EOC/INT SDO DGND DVDD CS A0 A1 A2 A3 CSTART AVDD AGND COMP REFM REFP AGND AVDD A7 A6 A5 A4 TLC3578, TLC2578 DW OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SCLK FS SDI EOC/INT SDO DGND DVDD CS A0 A1 CSTART AVDD AGND COMP REFM REFP AGND AVDD A3 A2 TLC3574, TLC2574 DW, N, OR PW PACKAGE (TOP VIEW) TLC3574, TLC3578, TLC2574, TLC2578 5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS SLAS262C − OCTOBER 2000 − REVISED MAY 2003 1 WWW.TI.COM D 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578 D Maximum Throughput 200-KSPS D Multiple Analog Inputs: − 8 Single-Ended Channels for TLC3578/2578 − 4 Single-Ended Channels for TLC3574/2574 D Analog Input Range: ±10 V D Pseudodifferential Analog Inputs D SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz D Built-In Conversion Clock and 8x FIFO D Single 5-V Analog Supply; 3-/5-V Digital Supply D Low-Power − 5.8 mA in Normal Operation − 20 µA in Power Down D Programmable Autochannel Sweep and Repeat D Hardware-Controlled, Programmable Sampling Period D Hardware Default Configuration D INL: TLC3574/78: ±1 LSB; TLC2574/78: ±0.5 LSB D DNL: TLC3574/78: ±0.5 LSB; TLC2574/78: ±0.5 LSB D SINAD: TLC3574/78: 79 dB; TLC2574/78: 72 dB D THD: TLC3574/78: −82 dB; TLC2574/78: −82 dB description The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host. Copyright 2000 − 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
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