전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD7819YR 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD7819YR
상세설명  2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
Download  11 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD7819YR 데이터시트(HTML) 6 Page - Analog Devices

Back Button AD7819YR Datasheet HTML 2Page - Analog Devices AD7819YR Datasheet HTML 3Page - Analog Devices AD7819YR Datasheet HTML 4Page - Analog Devices AD7819YR Datasheet HTML 5Page - Analog Devices AD7819YR Datasheet HTML 6Page - Analog Devices AD7819YR Datasheet HTML 7Page - Analog Devices AD7819YR Datasheet HTML 8Page - Analog Devices AD7819YR Datasheet HTML 9Page - Analog Devices AD7819YR Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 11 page
background image
REV. B
AD7819
–6–
CIRCUIT DESCRIPTION
Converter Operation
The AD7819 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Fig-
ures 2 and 3 below show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the sig-
nal on VIN+.
CHARGE
RESTRIBUTION
DAC
CONTROL
LOGIC
CLOCK
OSC
COMPARATOR
SW2
VDD/3
ACQUISITION
PHASE
SAMPLING
CAPACITOR
SW1
A
B
AGND
VIN
Figure 2. ADC Track Phase
When the ADC starts a conversion, see Figure 3, SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The Control Logic and the Charge Redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced the conversion is complete. The Control Logic generates
the ADC output code. Figure 7 shows the ADC transfer function.
CHARGE
RESTRIBUTION
DAC
CONTROL
LOGIC
CLOCK
OSC
COMPARATOR
SW2
VDD/3
CONVERSION
PHASE
SAMPLING
CAPACITOR
SW1
A
B
AGND
VIN
Figure 3. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7819. The
parallel interface is implemented using an 8-bit data bus, the
falling edge of
CONVST brings the BUSY signal high and at
the end of conversion, the falling edge of BUSY is used to
initiate an ISR on a microprocessor. (See Parallel Interface
section for more details.) VREF is connected to a well decoupled
VDD pin to provide an analog input range of 0 V to VDD. When
VDD is first connected the AD7819 powers up in a low current
mode, i.e., power-down. A rising edge on the
CONVST input
will cause the part to power up. (See Power-Up Times section.)
If power consumption is of concern, the automatic power-down
at the end of a conversion should be used to improve power
performance. See Power vs. Throughput Rate section of the
data sheet.
BUSY
RD
CS
CONVST
DB0-DB7
VDD
VREF
VIN
GND
AD7819
C/ P
PARALLEL
INTERFACE
0V TO VREF
INPUT
0.1 F
10 F
SUPPLY
2.7V TO 5.5V
Figure 4. Typical Connection Diagram
Analog Input
Figure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7819. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
20 mA is the maximum current these diodes can conduct with-
out causing irreversible damage to the part. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125
Ω. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
VIN
C2
4pF
D1
D2
R1
125
C1
3.5pF
VDD/3
CONVERT PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
Figure 5. Equivalent Analog Input Circuit
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the
CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on VIN is also being acquired during this
settling time. The minimum acquisition time needed is approxi-
mately 100 ns. Figure 6 shows the equivalent charging circuit
for the sampling capacitor when the ADC is in its acquisition
phase. R2 represents the source impedance of a buffer amplifier
or resistive network, R1 is an internal multiplexer resistance and
C1 is the sampling capacitor.
VIN
R1
125
R2
C1
3.5pF
Figure 6. Equivalent Sampling Circuit


유사한 부품 번호 - AD7819YR

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7819YR AD-AD7819YR Datasheet
146Kb / 11P
   2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
REV. A
AD7819YR AD-AD7819YR Datasheet
187Kb / 12P
   2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
logo
List of Unclassifed Man...
AD7819YR-REEL7 ETC2-AD7819YR-REEL7 Datasheet
34Kb / 1P
   8-BIT SAMPLING AD CONVERTER
AD7819YRREEL7 ETC2-AD7819YRREEL7 Datasheet
34Kb / 1P
   8-BIT SAMPLING AD CONVERTER
logo
Analog Devices
AD7819YRU AD-AD7819YRU Datasheet
146Kb / 11P
   2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
REV. A
More results

유사한 설명 - AD7819YR

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7819 AD-AD7819_15 Datasheet
156Kb / 11P
   2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
REV. B
AD7819 AD-AD7819_17 Datasheet
187Kb / 12P
   2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
AD7819 AD-AD7819 Datasheet
146Kb / 11P
   2.7 V to 5.5 V, 200 kSPS 8-Bit Sampling ADC
REV. A
AD7813 AD-AD7813_15 Datasheet
194Kb / 11P
   2.7 V to 5.5 V, 400 kSPS 8-/10-Bit Sampling ADC
REV. C
AD7813YNZ AD-AD7813YNZ Datasheet
174Kb / 11P
   2.7 V to 5.5 V, 400 kSPS 8-/10-Bit Sampling ADC
REV. C
AD7813 AD-AD7813_17 Datasheet
219Kb / 12P
   2.7 V to 5.5 V, 400 kSPS 8-/10-Bit Sampling ADC
AD7813 AD-AD7813 Datasheet
185Kb / 11P
   2.7 V to 5.5 V, 400 kSPS 8-/10-Bit Sampling ADC
REV. B
AD7811YRUZ AD-AD7811YRUZ Datasheet
211Kb / 19P
   2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs
REV. B
AD7811 AD-AD7811 Datasheet
200Kb / 19P
   2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs
REV. B
AD7812YRUZ AD-AD7812YRUZ Datasheet
211Kb / 19P
   2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs
REV. B
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com