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DAC7554IDGSG4 데이터시트(PDF) 4 Page - Texas Instruments |
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DAC7554IDGSG4 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 24 page www.ti.com TIMING CHARACTERISTICS (1) (2) SCLK SYNC DIN LD1 LD0 SEL1 SEL1 SEL1 SEL1 SEL0 D11 D1 D0 X t8 t4 t3 t2 t1 t7 t6 t5 DAC7554 SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 V DD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VDD = 2.7 V to 3.6 V 20 t1(3) SCLK cycle time ns VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 t2 SCLK HIGH time ns VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 t3 SCLK LOW time ns VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 4 SYNC falling edge to SCLK falling edge setup t4 ns time VDD = 3.6 V to 5.5 V 4 VDD = 2.7 V to 3.6 V 5 t5 Data setup time ns VDD = 3.6 V to 5.5 V 5 VDD = 2.7 V to 3.6 V 4.5 t6 Data hold time ns VDD = 3.6 V to 5.5 V 4.5 VDD = 2.7 V to 3.6 V 0 t7 SCLK falling edge to SYNC rising edge ns VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 20 t8 Minimum SYNC HIGH time ns VDD = 3.6 V to 5.5 V 20 (1) All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram Figure 1. (3) Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Figure 1. Serial Write Operation 4 |
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