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ADV7172KST 데이터시트(PDF) 8 Page - Analog Devices |
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ADV7172KST 데이터시트(HTML) 8 Page - Analog Devices |
8 / 60 page REV. B ADV7172/ADV7173 –8– t3 t2 t6 t1 t7 t5 t3 t4 t8 SDATA SCLOCK Figure 1. MPU Port Timing Diagram t9 t11 CLOCK PIXEL INPUT DATA t10 t12 HSYNC, FIELD/ VSYNC, BLANK Cb Y Cr Y Cb Y HSYNC, FIELD/ VSYNC, BLANK, CSO_HSO, VSO, CLAMP t13 t14 CONTROL I/PS CONTROL O/PS Figure 2. Pixel and Control Data Timing Diagram t16 t17 TTXREQ CLOCK TTX 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES 4 CLOCK CYCLES t18 Figure 3. Teletext Timing Diagram DAC Average Current Consumption DAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by RSET2/VREF (see Appendix 8). DAC A, B, C: In normal power mode the average current consumed by each DAC is the DAC output current as determined by RSET1 (see Appendix 8). In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by RSET1. Consult AN-551 for detailed information on ADV7172/ADV7173 power management. |
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