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SN74F112DG4 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74F112DG4 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 13 page SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 Copyright © 1993, Texas Instruments Incorporated 2–1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0 °C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H L LX X X H† H† H H ↓ LL Q0 Q0 H H ↓ HL H L H H ↓ LHL H H H ↓ H H Toggle H H H X X Q0 Q0 † The output levels in this configuration are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level. D OR N PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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