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FAN3180TSX 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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FAN3180TSX 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 18 page © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3180 • Rev. 1.0.3 2 Ordering Information Part Number Input Threshold UVLO (VON / VOFF) Package Packing Method Reel Quantity FAN3180TSX TTL 4.75 V / 4.55 V 5-Pin SOT23 Tape & Reel 3000 Functional Pin Configuration 1 4 5 3 2 IN+ VDD OUT GND 3V3 UVLO LDO Figure 2. Top View Thermal Characteristics (1) Package JL (2) JT (3) JA (4) JB (5) JT (6) Units 5-Pin SOT23 58 102 161 53 6 °C/W Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL ( JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT ( JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heat sink. 4. Theta_JA ( ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heat sink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB ( JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2. 6. Psi_JT ( JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. Pin Definitions Pin # Name Description 1 VDD Supply Voltage. Provides power to the IC. 2 GND Ground. Common ground reference for input and output circuits. 3 IN+ Non-Inverting Input. Connect to VDD to enable output. 4 3V3 3.3-V LDO Output with 15 mA output capability. 5 OUT Gate Drive Output. Held LOW unless required input is present and VDD is above UVLO threshold. |
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