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Si5376B-A-GL 데이터시트(PDF) 7 Page - Silicon Laboratories |
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Si5376B-A-GL 데이터시트(HTML) 7 Page - Silicon Laboratories |
7 / 66 page Si5376 Rev. 1.0 7 2-Level LVCMOS Input Pins Input Voltage Low VIL VDD =1.71V — — 0.5 V VDD =2.25V — — 0.7 V Input Voltage High VIH VDD =1.89V 1.4 — — V VDD =2.25V 1.8 — — V LVCMOS Output Pins Output Voltage Low VOL IO = 2 mA VDD =1.71V —— 0.4 V Output Voltage Low IO = 2 mA VDD =2.25V —— 0.4 V Output Voltage High VOH IO = –2 mA VDD =1.71V VDD – 0.4 —— V Output Voltage High IO = –2 mA VDD =2.25V VDD – 0.4 —— V Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Current draw is independent of supply voltage. 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD =2.5 V. 4. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. |
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