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AD7399BR 데이터시트(PDF) 4 Page - Analog Devices |
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AD7399BR 데이터시트(HTML) 4 Page - Analog Devices |
4 / 24 page AD7398/AD7399 Rev. C | Page 4 of 24 Parameter Symbol Condition 3 V to 5 V ± 10% ±5 V ± 10% Unit SUPPLY CHARACTERISTICS Shutdown Supply Current IDD_SD No load 30/60 30/60 μA typ/max Positive Supply Current IDD VIL = 0 V, no load, −40°C < TA < +125°C 1.5/2.8 1.6/3 mA typ/max IDD VIL = 0 V, no load, −40°C < TA < +85°C 1.5/2.6 1.6/2.8 mA typ/max Negative Supply Current ISS VIL = 0 V, no load 1.5/2.5 1.6/2.7 mA typ/max Power Dissipation PDISS VIL = 0 V, no load 5 16 mW typ Power Supply Sensitivity PSS ΔVDD = ±5% 0.006 0.006 %/% max 1 One LSB = VREF/4096 V for the 12-bit AD7398. 2 The first eight codes (000H to 007H) are excluded from the linearity error measurement in single-supply operation. 3 These parameters are guaranteed by design and not subject to production testing. 4 When VREF is connected to either the VDD or the VSS power supply, the corresponding VOUT voltage programs between ground and the supply voltage minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional information in the Theory of Operation section. 5 Input resistance is code dependent. 6 Typicals represent average readings measured at 25°C. 7 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 8 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. AD7399 10-BIT VOLTAGE OUTPUT DAC VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V; VREF = +2.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter Symbol Condition 3 V to 5 V ± 10% ±5 V ± 10% Unit STATIC PERFORMANCE Resolution1 N 10 10 Bits Relative Accuracy2 INL ±1 ±1 LSB max Differential Nonlinearity2 DNL Monotonic ±1 ±1 LSB max Zero-Scale Error VZSE Data = 000H 7 ±4 mV max Full-Scale Voltage Error VFSE Data = 3FFH ±15 ±15 mV max Full-Scale Tempco3 TCVFS 1.5 1.5 ppm/°C typ REFERENCE INPUT VREFIN Range4 VREF 0/VDD VSS/VDD V min/max Input Resistance5 RREF Data = 155H, worst case 40 40 kΩ typ6 Input Capacitance3 CREF 5 5 pF typ ANALOG OUTPUT Output Voltage Range VOUT 0 to VREF 0 to VREF V Output Current IOUT Data = 200H, ΔVOUT = 1 LSB ±5 ±5 mA typ Capacitive Load3 CL No oscillation 200 400 pF max LOGIC INPUTS Logic Input Low Voltage VIL VDD = 3 V 0.5 V max VDD = 5 V 0.8 0.8 V max Logic Input High Voltage VIH CLK only 80% VDD 4.0 V min 2.1 to 2.4 2.4 V min Input Leakage Current IIL 1 1 μA max Input Capacitance3 CIL 10 10 pF max INTERFACE TIMING3, 7 Clock Frequency fCLK 11 16.6 MHz max Clock Width High tCH 45 30 ns min Clock Width Low tCL 45 30 ns min CS to Clock Setup tCSS 10 5 ns min Clock to CS Hold tCSH 20 15 ns min Load DAC Pulse Width tLDAC 45 30 ns min Data Setup tDS 15 10 ns min Data Hold tDH 10 5 ns min Load Setup to CS tLDS 0 0 ns min Load Hold to CS tLDH 20 15 ns min |
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