전자부품 데이터시트 검색엔진 |
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CS401 데이터시트(PDF) 2 Page - Fujitsu Component Limited. |
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CS401 데이터시트(HTML) 2 Page - Fujitsu Component Limited. |
2 / 8 page CS401 Series 2 DS601-00001-2v0-E (Continued) • Support static timing sign-off. • Improve timing convergence by using Statistical Static Timing Analysis (SSTA). • Design For Manufacturing (DFM) enables stable product-supply and reduced variation. • Package lineup: FBGA, PBGA, TEBGA, FC-BGA Note: Including items under development. ■ MACRO LIBRARIES (INCLUDING MACROS CURRENTLY BEING PREPARED) 1. Logic cells (about 400 types) Library sets having four different threshold voltages of core transistors. • Adder • AND • AND-OR •AND-OR Inverter • Buffer • Clock-Buffer • Delay Buffer • ENOR • EOR •Inverter • Latch • NAND •NOR • OR • OR-AND • OR-AND Inverter • SCAN Flip flop • Non-SCAN Flip flop • Selector • Others 2. IP macros *: ARM, ARM7TDMI-S, ARM946E-S, ARM926EJ-S, ARM1176JZF-S, Cortex-M3, Coretex-R4F and Cortex-A9 are the trademarks of ARM Limited in the EU and other countries. 3. Special I/O interface macro CPU/DSP ARMTM* cores (ARM7TDMI-STM*, ARM946E-STM*, ARM926EJ-STM*, ARM1176JZF-STM*, Cortex-M3TM*, Cortex-R4FTM*, Cortex-A9TM* MPCore), Peripherals IP Mixed signal macro ADC, DAC, OPAMP, others Compiled macro SRAM (1 Port, 2 Port), ROM, product sum calculator, others PLL Analog PLL Special I/O LVDS, SSTL18, PCI, I2C Interface macro USB2.0 Device/host, Serial-ATA, PCI-Express, DDR2, HDMI, others |
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