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74AHC574PW 데이터시트(PDF) 11 Page - NXP Semiconductors |
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74AHC574PW 데이터시트(HTML) 11 Page - NXP Semiconductors |
11 / 18 page 74AHC_AHCT574_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 24 January 2008 11 of 18 NXP Semiconductors 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times mna803 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Qn output CP input Dn input Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times 001aah078 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH OE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM Table 8. Measurement points Type Input Output VM VM VX VY 74AHC574 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V 74AHCT574 1.5 V 0.5VCC VOL + 0.3 V VOH − 0.3 V |
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