전자부품 데이터시트 검색엔진 |
|
AD7303BR 데이터시트(PDF) 11 Page - Analog Devices |
|
AD7303BR 데이터시트(HTML) 11 Page - Analog Devices |
11 / 16 page AD7303 –11– REV. 0 POWER-ON RESET The AD7303 has a power-on reset circuit designed to allow output stability during power-up. This circuit holds the DACs in a reset state until a write takes place to the DAC. In the reset state all zeros are latched into the input registers of each DAC, and the DAC reg- isters are in transparent mode. Thus the output of both DACs are held at ground potential until a write takes place to the DAC. POWER-DOWN FEATURES Two bits in the control section of the 16-bit input word are used to put the AD7303 into low power mode. DAC A and DAC B can be powered down separately. When both DACs are powered down, the current consumption of the device is reduced to less than 1 µA, making the device suitable for use in portable battery powered equipment. The reference bias servo loop, the output amplifiers and associated linear circuitry are all shut down when the power- down is activated. The output sees a load of approximately 23 k Ω to GND when in power-down mode as shown in Figure 25. The contents of the data registers are unaffected when in power-down mode. The time to exit power-down is determined by the nature of the power-down, if the device is fully powered down the bias gen- erator is also powered down and the device takes typically 13 µs to exit power-down mode. If the device is only partially powered down, i.e., only one channel powered down, in this case the bias generator is active and the time required for the power-down chan- nel to exit this mode is typically 1.6 µs. See Figures 11 and 12. VO A/B VDD 11.7k Ω 11.7k Ω VREF IDAC Figure 25. Output Stage During Power-Down MICROPROCESSOR INTERFACING AD7303 to ADSP-2101/ADSP-2103 Interface Figure 26 shows a serial interface between the AD7303 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-Bit Word Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each falling edge of the serial clock and clocked into the AD7303 on the rising edge of the SCLK. SCLK ADSP-2101/ ADSP-2103* DT *ADDITIONAL PINS OMITTED FOR CLARITY SYNC DIN SCLK AD7303* TFS Figure 26. AD7303 to ADSP-2101/ADSP-2103 Interface AD7303 to 68HC11/68L11 Interface Figure 27 shows a serial interface between the AD7303 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the CLKIN of the AD7303, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for cor- rect operation of this interface are as follows: the 68HC11/ 68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 0. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the rising edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD7303, PC7 is left low after the first eight bits are transferred, and a second serial write op- eration is performed to the DAC and PC7 is taken high at the end of this procedure. SCLK 68HC11/68L11* SCK *ADDITIONAL PINS OMITTED FOR CLARITY SYNC DIN MOSI AD7303* PC7 Figure 27. AD7303 to 68HC11/68L11 Interface AD7303 to 80C51/80L51 Interface Figure 28 shows a serial interface between the AD7303 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD7303, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case port line P3.3 is used. When data is to be transmit- ted to the AD7303, P3.3 is taken low. The 80C51/80L51 trans- mits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ 80L51 outputs the serial data in a format which has the LSB first. The AD7303 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. SCLK 80C51/80L51* TXD *ADDITIONAL PINS OMITTED FOR CLARITY SYNC SDIN RXD AD7303* P3.3 Figure 28. AD7303 to 80C51/80L51 Interface |
유사한 부품 번호 - AD7303BR |
|
유사한 설명 - AD7303BR |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |