전자부품 데이터시트 검색엔진 |
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AD7712AR 데이터시트(PDF) 6 Page - Analog Devices |
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AD7712AR 데이터시트(HTML) 6 Page - Analog Devices |
6 / 28 page REV. F –6– AD7712 Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments External Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 tCLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t24 7 4 tCLK IN ns max Data Access Time ( RFS Low to Data Valid) t25 7 10 ns min SCLK Falling Edge to Data Valid Delay 2 tCLK IN + 20 ns max t26 2 tCLK IN ns min SCLK High Pulse Width t27 2 tCLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t29 8 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS/TFS to SCLK Falling Edge Hold Time t31 8 5 tCLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 tCLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 tCLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. Specifications subject to change without notice. TO OUTPUT PIN 2.1V 1.6mA 200 A 100pF Figure 1. Load Circuit for Access Time and Bus Relinquish Time PIN CONFIGURATION DIP and SOIC TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 AD7712 AVDD VSS TP STANDBY AIN1(–) MCLK IN MCLK OUT A0 AIN1(+) MODE SCLK SYNC VBIAS REF IN(–) REF IN(+) REF OUT AIN2 DGND DVDD SDATA DRDY AGND TFS RFS TIMING CHARACTERISTICS (continued) |
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