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AD7862ARS-10 데이터시트(PDF) 8 Page - Analog Devices |
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AD7862ARS-10 데이터시트(HTML) 8 Page - Analog Devices |
8 / 16 page AD7862 –8– REV. 0 currents, as the resistor stage is followed by a high input impedance stage of the track/hold amplifier. For the AD7862-10, R1 = 30 k Ω, R2 = 7.5 kΩ, and R3 = 10 kΩ. For the AD7862-3, R1 = R2 = 6.5 k Ω and R3 is open circuit. For the AD7862-10 and AD7862-3, the designed code transi- tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs, 3 LSBs . . .). Output coding is twos complement binary with 1 LSB = FS/4096. The ideal input/output transfer function for the AD7862-10 and AD7862-3 is shown in Table I. Table I. Ideal Input/Output Code Table for the AD7862-10/-3 Analog Inputl Digital Output Code Transition +FSR/2 – 1 LSB 2 011 . . . 110 to 011 . . . 111 +FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110 +FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101 GND + 1 LSB 000 . . . 000 to 000 . . . 001 GND 111 . . . 111 to 000 . . . 000 GND – 1 LSB 111 . . . 110 to 111 . . . 111 –FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011 –FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010 –FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001 NOTES 1FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with REF IN = +2.5 V. 21 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with REF IN = +2.5 V. The analog input section for the AD7862-2 contains no biasing resistors, and the VAX/BX pin drives the input to the multiplexer and track/hold amplifier circuitry directly. The analog input range is 0 V to +2.5 V into a high impedance stage with an input current of less than 500 nA. This input is benign with no dynamic charging currents. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FS/4096 = 2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output transfer function for the AD7862-2. Table II. Ideal Input/Output Code Table for the AD7862-2 Analog Input 1 Digital Output Code Transition +FSR – 1 LSB 2 111 . . . 110 to 111 . . . 111 +FSR – 2 LSB 111 . . . 101 to 111 . . . 110 +FSR – 3 LSB 111 . . . 100 to 111 . . . 101 GND + 3 LSB 000 . . . 010 to 000 . . . 011 GND + 2 LSB 000 . . . 001 to 000 . . . 010 GND + 1 LSB 000 . . . 000 to 000 . . . 001 NOTES 1FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V. 21 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V. OFFSET AND FULL-SCALE ADJUSTMENT In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications will require the input signal to span the full analog input dynamic range. In such applications, offset and full-scale error will have to be adjusted to zero. Figure 4 shows a circuit that can be used to adjust the offset and full-scale errors on the AD7862 (VA1 on the AD7862-10 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7862 while the input voltage is a 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of –2.44 mV (–1/2 LSB) at VA1 (see Figure 4) and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000. V1 R1 10k Ω R2 500 Ω R3 10k Ω AGND AD7862* *ADDITIONAL PINS OMITTED FOR CLARITY INPUT RANGE = ±10V 10k Ω R5 10k Ω R4 VA1 Figure 4. Full-Scale Adjust Circuit Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows: Positive Full-Scale Adjust Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at VA1. Adjust R2 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111. Negative Full-Scale Adjust Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at VA1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. An alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels will ensure small full-scale errors on the other channels. TIMING AND CONTROL Figure 5a shows the timing and control sequence required to obtain optimum performance (Mode 1) from the AD7862. In the sequence shown, a conversion is initiated on the falling edge of CONVST. This places both track/holds into hold simulta- neously, and new data from this conversion is available in the output register of the AD7862 3.6 µs later. The BUSY signal indicates the end of conversion, and at this time the conversion results for both inputs are available to be read. A second conversion is then initiated. If the multiplexer select A0 is low, the first and second read pulses after the first conversion accesses the result from channel A (VA1 and VA2 respectively). The third |
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