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AM28F010A-120FE 데이터시트(PDF) 8 Page - Advanced Micro Devices |
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AM28F010A-120FE 데이터시트(HTML) 8 Page - Advanced Micro Devices |
8 / 35 page 8 Am28F010A BASIC PRINCIPLES This section contains descriptions about the device read, erase, and program operations, and write opera- tion status of the Am29FxxxA, 12.0 volt family of Flash devices. References to some tables or figures may be given in generic form, such as “Command Definitions table”, rather than “Table 1”. Refer to the corresponding data sheet for the actual table or figure. The Am28FxxxA family uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input. Read Only Memory Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes. Command Register The command register is enabled only when high volt- age is applied to the VPP pin. The erase and repro- gramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The tradi- tional read, standby, output disable, and Auto select modes are available via the register. The device’s command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device opera- tions. For system design simplification, the device is de- signed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# which- ever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with re- spect to the WE# signal. OVERVIEW OF ERASE/PROGRAM OPERATIONS Embedded Erase Algorithm AMD now makes erasure extremely simple and reli- able. The Embedded Erase algorithm requires the user to only write an erase setup command and erase com- mand. The device will automatically pre-program and verify the entire array. The device automatically times the erase pulse width, provides the erase verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the erase operation. Embedded Programming Algorithm AMD now makes programming extremely simple and reliable. The Embedded Programming algorithm re- quires the user to only write a program setup command and a program command. The device automatically times the programming pulse width, provides the pro- gram verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the programming operation. DATA PROTECTION The device is designed to offer protection against acci- dental erasure or programming caused by spurious system level signals that may exist during power transi- tions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. The device also incorporates several features to pre- vent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for VCC < VLKO (see DC characteristics section for volt- ages). When VCC < VLKO, the command register is dis- abled, all internal program/erase circuits are disabled, and the device resets to the read mode. The device ig- nores all writes until VCC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent unintentional writes. Write Pulse “Glitch” Protection Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE# = VIL, CE# =VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit Power-up of the device with WE# = CE# = VIL and OE# = VIH will not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. |
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